Fractional-N Frequency Synthesizer Data Sheet ADF4154 FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz The ADF4154 is a fractional-N frequency synthesizer that 2.7 V to 3.3 V power supply implements local oscillators in the up conversion and down Separate V allows extended tuning voltage P conversion sections of wireless receivers and transmitters. It Programmable dual-modulus prescaler 4/5, 8/9 consists of a low noise digital phase frequency detector (PFD), Programmable charge pump currents a precision charge pump, and a programmable reference divider. 3-wire serial interface There is a - based fractional interpolator to allow programmable Digital lock detect fractional-N division. The INT, FRAC, and MOD registers define Power-down mode an overall N-divider (N = (INT + (FRAC/MOD))). In addition, Pin compatible with the ADF4110/ADF4111/ the 4-bit reference counter (R-counter) allows selectable REF IN ADF4112/ADF4113, ADF4106, ADF4153 frequencies at the PFD input. A complete phase-locked loop (PLL) Programmable modulus on fractional-N synthesizer can be implemented if the synthesizer is used with an external Trade-off noise vs. spurious performance loop filter and a voltage-controlled oscillator (VCO). Fast-lock mode with built-in timer A key feature of the ADF4154 is the fast-lock mode with a built- Loop filter design possible with ADIsimPLL in timer. The user can program a predetermined countdown time value so that the PLL remains in wide bandwidth mode, APPLICATIONS instead of the user having to control this time externally. Base stations for mobile radio (WiMAX, PHS, GSM, PCS, DCS, CDMA, PMR, W-CDMA, supercell 3G) Control of all on-chip registers is via a simple 3-wire interface. Wireless handsets (PMR, GSM, PCS, DCS, CDMA, WCDMA) The device operates with a power supply ranging from 2.7 V to CATV equipment 3.3 V and can be powered down when not in use. Wireless LANs Communications test equipment FUNCTIONAL BLOCK DIAGRAM AV DV V SDV R DD DD P DD SET ADF4154 REFERENCE 4-BIT + PHASE 2 R COUNTER REF IN FREQUENCY CHARGE DOUBLER DETECTOR PUMP CP V DD HIGH Z DGND LOCK DETECT CURRENT SETTING OUTPUT MUXOUT FAST-LOCK MUX SWITCH V RFCP3 RFCP2 RFCP1 DD R DIV RF A IN N DIV N COUNTER RF B IN THIRD ORDER FRACTIONAL INTERPOLATOR FRACTION MODULUS INTEGER REG REG REG CLOCK 24-BIT DATA DATA REGISTER LE AGND DGND CPGND Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Trademarks and registered trademarks are the property of their respective owners. 04833-001ADF4154 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Definitions ................................................................... 16 Applications ....................................................................................... 1 R-Divider Register, R1 ............................................................... 16 General Description ......................................................................... 1 Control Register, R2 ................................................................... 16 Functional Block Diagram .............................................................. 1 Noise and Spur Register, R3 ...................................................... 17 Revision History ............................................................................... 2 Reserved Bits ............................................................................... 17 Specifications ..................................................................................... 3 Initialization Sequence .............................................................. 18 Timing Characteristics ................................................................ 4 RF Synthesizer: A Worked Example ........................................ 18 Absolute Maximum Ratings ............................................................ 5 Modulus ....................................................................................... 18 ESD Caution .................................................................................. 5 Reference Doubler and Reference Divider ............................. 18 Pin Configuration and Pin Function Descriptions ...................... 6 12-Bit Programmable Modulus ................................................ 18 Typical Performance Characteristics ............................................. 7 Spurious Optimization and Fast Lock ..................................... 18 Circuit Description ........................................................................... 9 Fast-Lock Timer and Register Sequences ............................... 19 Reference Input Section ............................................................... 9 Fast Lock: An Example .............................................................. 19 RF Input Stage ............................................................................... 9 Fast Lock: Loop Filter Topology ............................................... 19 RF INT Divider ............................................................................. 9 Spur Mechanisms ....................................................................... 19 INT, FRAC, MOD, and R Relationship ..................................... 9 Spur Consistency ........................................................................ 20 R-Counter ...................................................................................... 9 Filter DesignADIsimPLL ....................................................... 20 Phase Frequency Detector (PFD) and Charge Pump .............. 9 Interfacing ................................................................................... 20 MUXOUT and Lock Detect ...................................................... 10 PCB Design Guidelines for Chip Scale Package .................... 21 Input Shift Registers ................................................................... 10 Outline Dimensions ....................................................................... 22 Program Modes .......................................................................... 10 Ordering Guide .......................................................................... 22 Registers ........................................................................................... 11 REVISION HISTORY 8/12Rev. B to Rev. C Changes to Figure 13 ......................................................................... 8 Changes to R-Divider Register Map ............................................ 13 Changes to Figure 4 .......................................................................... 6 Changes to Control Register Map ................................................ 14 Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) .... 22 Change to REFIN Doubler Section ................................................ 18 Changes to Ordering Guide .......................................................... 22 Added Initialization Sequence Section ........................................ 18 9/11Rev. A to Rev. B Change to 12-Bit Programmable Modulus Section ................... 18 Changes to Noise Characteristics Parameter ................................ 3 Changes to Fast-Lock Timer and Register Sequences Section ........ 19 Updated Outline Dimensions ....................................................... 22 Changes to Fast Lock: Loop Filter Topology Section ................ 19 Changes to Ordering Guide .......................................................... 22 Deleted Spurious Signal Section ................................................... 18 12/06Rev. 0 to Rev. A Added Spur Mechanisms Section ................................................ 19 Changes to Features .......................................................................... 1 Added Spur Consistency Section ................................................. 20 Changes to Applications .................................................................. 1 Change to Filter DesignADIsimPLL Section .......................... 20 Changes to Functional Block Diagram .......................................... 1 Change to Interfacing Section ...................................................... 20 Changes to Specifications ................................................................ 3 Updated Outline Dimensions ....................................................... 22 Changes to Absolute Maximum Ratings ....................................... 5 Changes to Ordering Guide .......................................................... 22 Changes to Typical Performance Characteristics Conditions .... 7 5/04Revision 0: Initial Version Replaced Figure 5 through Figure 7 ............................................... 7 Rev. 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