Integer-N/Fractional-N PLL Synthesizer Data Sheet ADF4155 FEATURES GENERAL DESCRIPTION Input frequency range: 500 MHz to 8000 MHz The ADF4155 allows implementation of fractional-N or Fractional-N synthesizer and integer-N synthesizer integer-N phase-locked loop (PLL) frequency synthesizers Phase frequency detector (PFD) up to 125 MHz when used with an external loop filter, external voltage High resolution 38-bit modulus controlled oscillator (VCO), and external reference frequency. Separate charge pump supply (V ) allows extended tuning P The ADF4155 is for use with external VCO parts up to an voltage in 5 V systems 8 GHz operating frequency. The high resolution programmable Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output modulus allows synthesis of exact frequencies with 0 Hz error. Differential and single-ended reference inputs The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to Power supply: 3.3 V 5% allow the user to generate RF output frequencies as low as Logic compatibility: 1.8 V 7.8125 MHz. Programmable dual-modulus prescaler (P) of 4/5 or 8/9 Programmable output power level Control of all on-chip registers is through a simple 3-wire 3-wire serial interface interface. The device operates with a nominal power supply of Analog and digital lock detect 3.3 V 5% and can be powered down when not in use. APPLICATIONS The ADF4155 is available in a 24-lead, 4 mm 4 mm LFCSP package. Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Test equipment Wireless LANs, CATV equipment Clock generation FUNCTIONAL BLOCK DIAGRAM AV DV V RFV R DD DD P DD SET MULTIPLEXER MUXOUT 10-BIT R 2 REF + IN 2 COUNTER DIVIDER DOUBLER LOCK REF IN DETECT CLK DATA REGISTER DATA FUNCTION CHARGE CP OUT LE LATCH PUMP PHASE COMPARATOR CE C 1 REG C 2 REG ADF4155 INTEGER FRACTION MODULUS REG REG REG RF + OUT OUTPUT THIRD-ORDER 1/2/4/8/16/32/64 FRACTIONAL STAGE RF OUT INTERPOLATOR PDB RF N COUNTER RF + INPUT IN STAGE RF IN A D CP RF GND GND GND GND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12262-001ADF4155 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Maps .................................................................................. 15 Applications ....................................................................................... 1 Register 0 ..................................................................................... 17 General Description ......................................................................... 1 Register 1 ..................................................................................... 18 Functional Block Diagram .............................................................. 1 Register 2 ..................................................................................... 19 Revision History ............................................................................... 2 Register 3 ..................................................................................... 19 Specifications ..................................................................................... 3 Register 4 ..................................................................................... 20 Timing Characteristics ................................................................ 5 Register 5 ..................................................................................... 22 Absolute Maximum Ratings ............................................................ 6 Register 6 ..................................................................................... 23 Transistor Count ........................................................................... 6 Register 7 ..................................................................................... 24 ESD Caution .................................................................................. 6 Register 8 ..................................................................................... 25 Pin Configuration and Function Descriptions ............................. 7 Register Initialization Sequence ............................................... 26 Typical Performance Characteristics ............................................. 9 RF SynthesizerA Worked Example ...................................... 26 Circuit Description ......................................................................... 12 Reference Doubler and Reference Divider ............................. 27 Reference Input Section ............................................................. 12 Cycle Slip Reduction for Faster Lock Times ........................... 27 RF N Counter .............................................................................. 12 Spurious Optimization .............................................................. 27 Phase Frequency Detector and Charge Pump ........................... 13 Spur Mechanisms ....................................................................... 27 MUXOUT and Lock Detect ...................................................... 13 Applications Information .............................................................. 28 Input Shift Registers ................................................................... 13 Local Oscillator with RF Buffer ................................................ 28 Program Modes .......................................................................... 13 Outline Dimensions ....................................................................... 29 Output Stage ................................................................................ 14 Ordering Guide .......................................................................... 29 REVISION HISTORY 4/14Revision 0: Initial Version Rev. 0 Page 2 of 32