High Resolution 6 GHz Fractional-N Frequency Synthesizer Data Sheet ADF4157 FEATURES GENERAL DESCRIPTION RF bandwidth to 6 GHz The ADF4157 is a 6 GHz fractional-N frequency synthesizer with 25-bit fixed modulus allows subhertz frequency resolution a 25-bit fixed modulus, allowing subhertz frequency resolution 2.7 V to 3.3 V power supply at 6 GHz. It consists of a low noise digital phase frequency detector Separate V allows extended tuning voltage (PFD), a precision charge pump, and a programmable reference P Programmable charge pump currents divider. There is a - based fractional interpolator to allow 3-wire serial interface programmable fractional-N division. The INT and FRAC values 25 Digital lock detect define an overall N divider, N = INT + (FRAC/2 ). The ADF4157 Power-down mode features cycle slip reduction circuitry, which leads to faster lock Pin compatible with the following frequency synthesizers: times without the need for modifications to the loop filter. ADF4110/ADF4111/ADF4112/ADF4113/ Control of all on-chip registers is via a simple 3-wire interface. ADF4106/ADF4153/ADF4154/ADF4156 The device operates with a power supply ranging from 2.7 V to Cycle slip reduction for faster lock times 3.3 V and can be powered down when not in use. APPLICATIONS Satellite communications terminals, radar equipment Instrumentation equipment Personal mobile radio (PMR) Base stations for mobile radio Wireless handsets FUNCTIONAL BLOCK DIAGRAM AV DV V R DD DD P SET ADF4157 REFERENCE 5-BIT 2 REF R COUNTER IN DOUBLER 2 + DIVIDER PHASE CP CHARGE FREQUENCY PUMP DETECTOR V DD HIGH Z DGND CSR LOCK CURRENT DETECT SETTING OUTPUT MUXOUT SD OUT MUX V DD RFCP4 RFCP3 RFCP2 RFCP1 R DIV RF A IN N COUNTER N DIV RF B IN THIRD-ORDER FRACTIONAL INTERPOLATOR CE CLK FRACTION MODULUS INTEGER 32-BIT DATA REG 25 REG 2 DATA REGISTER LE AGND DGND CPGND Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20072012 Analog Devices, Inc. All rights reserved. 05874-001ADF4157 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Program Modes .......................................................................... 10 Applications ....................................................................................... 1 Register Maps .................................................................................. 11 General Description ......................................................................... 1 FRAC/INT Register (R0) Map.................................................. 12 Functional Block Diagram .............................................................. 1 LSB FRAC Register (R1) Map .................................................. 13 Revision History ............................................................................... 2 R Divider Register (R2) Map .................................................... 14 Specif icat ions ..................................................................................... 3 Function Register (R3) Map ..................................................... 16 Timing Specifications .................................................................. 4 Test Register (R4) Map .............................................................. 17 Absolute Maximum Ratings ............................................................ 5 Applications Information .............................................................. 18 Thermal Resistance ...................................................................... 5 Initialization Sequence .............................................................. 18 ESD Caution .................................................................................. 5 RF Synthesizer: A Worked Example ........................................ 18 Pin Configurations and Function Descriptions ........................... 6 Reference Doubler and Reference Divider ............................. 18 Typical Performance Characteristics ............................................. 8 Cycle Slip Reduction for Faster Lock Times ........................... 18 Circuit Description ........................................................................... 9 Fastlock Timer and Register Sequences .................................. 19 Reference Input Section ............................................................... 9 Fastlock: An Example ................................................................ 19 RF Input Stage ............................................................................... 9 Fastlock: Loop Filter Topology ................................................. 19 RF INT Divider ............................................................................. 9 Spur Mechanisms ....................................................................... 19 25-Bit Fixed Modulus .................................................................. 9 Low Frequency Applications .................................................... 20 INT, FRAC, and R Relationship ................................................. 9 Filter DesignADIsimPLL ....................................................... 20 RF R Counter ................................................................................ 9 Operating with Wide Loop Filter Bandwidths ....................... 20 Phase Frequency Detector (PFD) and Charge Pump ............ 10 PCB Design Guidelines for the Chip Scale Package .............. 20 MUXOUT and Lock Detect ...................................................... 10 Outline Dimensions ....................................................................... 21 Input Shift Register..................................................................... 10 Ordering Guide .......................................................................... 21 REVISION HISTORY 8/12Rev. C to Rev. D Changes to Figure 4 and Table 5 ...................................................... 6 Changes to Figure 15 ...................................................................... 10 Changes to Figure 4 and Table 5 ...................................................... 6 Changes to Figure 16 ...................................................................... 11 Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) ..... 22 Changes to Figure 17 ...................................................................... 12 Changes to Ordering Guide ........................................................... 21 Changes to Figure 19 ...................................................................... 15 Criticizing Added Negative Bleed Current Section, CLK Divider Mode 3/12Rev. B to Rev. C Section, and 12-Bit Clock Divider Value Section....................... 17 Changes to Reserved Bits Section and Figure 21 ....................... 17 Changes to Table 1 ............................................................................ 3 Deleted Interfacing Section ........................................................... 18 Changes to Ordering Guide .......................................................... 21 Added Fastlock Timer and Register Sequences Section, 9/11Rev. A to Rev. B Fastlock: An Example Section, and Fastlock: Loop Filter Changes to Noise Characteristics Parameter ................................ 3 Topology Section ............................................................................ 19 Changes to EPAD Note .................................................................... 6 Added Figure 22 and Figure 23 Renumbered Sequentially ..... 19 Added Operating with Wide Loop Filter Bandwidths 1/09Rev. 0 to Rev. A S ection .............................................................................................. 20 Changes to Figure 1 .......................................................................... 1 Updated Outline Dimensions ....................................................... 21 Changes to Reference Characteristics Parameter, Table 1 .......... 3 7/07Revision 0: Initial Version Changes to Table 3 ............................................................................ 5 Rev. D Page 2 of 24