Direct Modulation/Waveform Generating, 6.1 GHz, Fractional-N Frequency Synthesizer Data Sheet ADF4158 FEATURES GENERAL DESCRIPTION Radio frequency (RF) bandwidth to 6.1 GHz The ADF4158 is a 6.1 GHz, fractional-N frequency synthesizer 25-bit fixed modulus allows subhertz frequency resolution with direct modulation and waveform generation capability. It Frequency and phase modulation capability contains a 25-bit fixed modulus, allowing subhertz resolution at Sawtooth and triangular waveforms in the frequency domain 6.1 GHz. It consists of a low noise digital phase frequency Parabolic ramp detector (PFD), a precision charge pump, and a programmable Ramp superimposed with FSK reference divider. There is a sigma-delta (-) based fractional Ramp with 2 different sweep rates interpolator to allow programmable fractional-N division. The Ramp delay INT and FRAC registers define an overall N-divider as N = INT + 25 Ramp frequency readback (FRAC/2 ). Ramp interruption The ADF4158 can be used to implement frequency shift keying 2.7 V to 3.3 V power supply (FSK) and phase shift keying (PSK) modulation. There are also Separate V allows extended tuning voltage P a number of frequency sweep modes available that generate Programmable charge pump currents various waveforms in the frequency domain, for example, 3-wire serial interface sawtooth and triangular waveforms. The ADF4158 features Digital lock detect cycle slip reduction circuitry, which leads to faster lock times, Power-down mode without the need for modifications to the loop filter. Cycle slip reduction for faster lock times Control of all on-chip registers is via a simple 3-wire interface. Switched bandwidth fast lock mode The device operates with a power supply ranging from 2.7 V to Qualified for automotive applications 3.3 V and can be powered down when not in use. APPLICATIONS Frequency modulated continuous wave (FMCW) radar Communications test equipment FUNCTIONAL BLOCK DIAGRAM AV DV V R DD DD P SET ADF4158 SW2 REFERENCE 5-BIT 2 R-COUNTER REF IN DOUBLER 2 + DIVIDER PHASE CHARGE CP FREQUENCY PUMP DETECTOR V DD HIGH-Z CSR DGND LOCK DETECT SW1 FL SWITCH OUTPUT O MUXOUT V DD MUX R DIV N DIV RF A CE IN N-COUNTER TX DATA RF B IN THIRD-ORDER FRACTIONAL INTERPOLATOR CLK MODULUS FRACTION INTEGER 32-BIT 25 DATA REG 2 REG DATA REGISTER LE AGND DGND CPGND Figure 1. Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08728-001ADF4158 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 R-Divider Register (R2) Map .................................................... 17 Applications ....................................................................................... 1 Function Register (R3) Map ...................................................... 19 General Description ......................................................................... 1 Test Register (R4) Map .............................................................. 21 Functional Block Diagram .............................................................. 1 Deviation Register (R5) Map .................................................... 22 Revision History ............................................................................... 3 Step Register (R6) Map .............................................................. 23 Specifications ..................................................................................... 4 Delay Register (R7) Map ........................................................... 24 Timing Specifications .................................................................. 5 Applications Information .............................................................. 25 Absolute Maximum Ratings ............................................................ 7 Initialization Sequence............................................................... 25 ESD Caution .................................................................................. 7 RF Synthesizer: A Worked Example ........................................ 25 Pin Configuration and Pin Function Descriptions ...................... 8 Reference Doubler and Reference Divider ............................. 25 Typical Performance Characteristics ............................................. 9 Cycle Slip Reduction for Faster Lock Times ........................... 25 Circuit Description ......................................................................... 11 Modulation .................................................................................. 26 Reference Input Section ............................................................. 11 Waveform Generation ............................................................... 26 RF Input Stage ............................................................................. 11 Other Waveforms ....................................................................... 28 RF INT Divider ........................................................................... 11 External Control of Ramp Steps ............................................... 30 25-Bit Fixed Modulus ................................................................ 11 Fast Lock Mode ........................................................................... 32 INT, FRAC, and R Relationship ............................................... 11 Spur Mechanisms ....................................................................... 33 R-Counter .................................................................................... 12 Low Frequency Applications .................................................... 33 Phase Frequency Detector (PFD) and Charge Pump ............ 12 Filter DesignADIsimPLL ....................................................... 33 MUXOUT and LOCK Detect ................................................... 12 PCB Design Guidelines for the Chip Scale Package .............. 33 Input Shift Registers ................................................................... 12 Application of ADF4158 in FMCW Radar ................................. 34 Program Modes .......................................................................... 12 Outline Dimensions ....................................................................... 35 Register Maps .................................................................................. 13 Ordering Guide ........................................................................... 35 FRAC/INT Register (R0) Map .................................................. 15 Automotive Products ................................................................. 35 LSB FRAC Register (R1) Map ................................................... 16 Rev. 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