Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer Data Sheet ADF4159 FEATURES GENERAL DESCRIPTION RF bandwidth to 13 GHz The ADF4159 is a 13 GHz, fractional-N frequency synthesizer High and low speed FMCW ramp generation with modulation and both fast and slow waveform generation 25-bit fixed modulus allows subhertz frequency resolution capability. The part uses a 25-bit fixed modulus, allowing subhertz PFD frequencies up to 110 MHz frequency resolution. Normalized phase noise floor of 224 dBc/Hz The ADF4159 consists of a low noise digital phase frequency FSK and PSK functions detector (PFD), a precision charge pump, and a programmable Sawtooth, triangular, and parabolic waveform generation reference divider. The --based fractional interpolator allows Ramp superimposed with FSK programmable fractional-N division. The INT and FRAC registers Ramp with 2 different sweep rates 25 define an overall N divider as N = INT + (FRAC/2 ). Ramp delay, frequency readback, and interrupt functions The ADF4159 can be used to implement frequency shift keying Programmable phase control (FSK) and phase shift keying (PSK) modulation. Frequency sweep 2.7 V to 3.45 V analog power supply modes are also available to generate various waveforms in the 1.8 V digital power supply frequency domain, for example, sawtooth and triangular wave- Programmable charge pump currents forms. Sweeps can be set to run automatically or with each step 3-wire serial interface manually triggered by an external pulse. The ADF4159 features Digital lock detect cycle slip reduction circuitry, which enables faster lock times ESD performance: 3000 V HBM, 1000 V CDM without the need for modifications to the loop filter. Qualified for automotive applications Control of all on-chip registers is via a simple 3-wire interface. The APPLICATIONS ADF4159 operates with an analog power supply in the range of FMCW radars 2.7 V to 3.45 V and a digital power supply in the range of 1.62 V Communications test equipment to 1.98 V. The device can be powered down when not in use. Communications infrastructure FUNCTIONAL BLOCK DIAGRAM AV DV SDV V R DD DD DD P SET ADF4159 SW2 REFERENCE 5-BIT 2 REF R COUNTER IN DOUBLER 2 + DIVIDER PHASE CP CHARGE FREQUENCY PUMP DETECTOR HIGH-Z CSR DGND LOCK DETECT FAST LOCK SW1 OUTPUT SWITCH MUXOUT SD OUT MUX DV DD R DIV + RF A IN N COUNTER N DIV RF B IN THIRD-ORDER CE FRACTIONAL INTERPOLATOR TX DATA CLK FRACTION MODULUS INTEGER 32-BIT 25 DATA VALUE 2 VALUE VALUE DATA REGISTER LE AGND DGND SDGND CPGND Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 10849-001ADF4159 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Step Register (R6) Map .............................................................. 23 Applications ....................................................................................... 1 Delay Register (R7) Map ........................................................... 24 General Description ......................................................................... 1 Applications Information .............................................................. 25 Functional Block Diagram .............................................................. 1 Initialization Sequence .............................................................. 25 Revision History ............................................................................... 3 RF Synthesizer Worked Example ............................................. 25 Specifications ..................................................................................... 4 Reference Doubler ...................................................................... 25 Timing Specifications .................................................................. 5 Cycle Slip Reduction for Faster Lock Times ........................... 25 Absolute Maximum Ratings ............................................................ 7 Modulation .................................................................................. 26 Thermal Resistance ...................................................................... 7 Waveform Generation ............................................................... 26 ESD Caution .................................................................................. 7 Waveform Deviations and Timing ........................................... 27 Pin Configuration and Function Descriptions ............................. 8 Single Ramp Burst ...................................................................... 27 Typical Performance Characteristics ............................................. 9 Single Triangular Burst .............................................................. 27 Theory of Operation ...................................................................... 11 Single Sawtooth Burst ................................................................ 27 Reference Input Section ............................................................. 11 Sawtooth Ramp........................................................................... 27 RF Input Stage ............................................................................. 11 Triangular Ramp ........................................................................ 27 RF INT Divider ........................................................................... 11 FMCW Radar Ramp Settings Worked Example ...................... 27 25-Bit Fixed Modulus ................................................................ 11 Activating the Ramp .................................................................. 28 INT, FRAC, and R Counter Relationship ................................ 11 Other Waveforms ....................................................................... 28 R Counter .................................................................................... 11 Ramp Complete Signal to MUXOUT ..................................... 31 Phase Frequency Detector (PFD) and Charge Pump ............ 12 External Control of Ramp Steps ............................................... 31 MUXOUT and Lock Detect ...................................................... 12 Interrupt Modes and Frequency Readback ............................ 32 Input Shift Register..................................................................... 12 Fast Lock Mode .......................................................................... 33 Program Modes .......................................................................... 12 Spur Mechanisms ....................................................................... 34 Register Maps .................................................................................. 13 Filter Design Using ADIsimPLL .............................................. 34 FRAC/INT Register (R0) Map .................................................. 15 PCB Design Guidelines for the Chip Scale Package .............. 34 LSB FRAC Register (R1) Map ................................................... 16 Application of the ADF4159 in FMCW Radar........................... 35 R Divider Register (R2) Map .................................................... 17 Outline Dimensions ....................................................................... 36 Function Register (R3) Map ...................................................... 19 Ordering Guide .......................................................................... 36 Clock Register (R4) Map ........................................................... 21 Automotive Products ................................................................. 36 Deviation Register (R5) Map .................................................... 22 Rev. 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