Direct Modulation/Fast Waveform Generating, 13.5 GHz, Fractional-N Frequency Synthesizer Data Sheet ADF4169 FEATURES GENERAL DESCRIPTION RF bandwidth to 13.5 GHz The ADF4169 is a 13.5 GHz, fractional-N frequency synthesizer High and low speed FMCW ramp generation with modulation and both fast and slow waveform generation 25-bit fixed modulus allows subhertz frequency resolution capability. The device uses a 25-bit fixed modulus, allowing PFD frequencies up to 130 MHz subhertz frequency resolution. Normalized phase noise floor of 224 dBc/Hz The ADF4169 consists of a low noise digital phase frequency FSK and PSK functions detector (PFD), a precision charge pump, and a programmable Sawtooth and triangular waveform generation reference divider. The --based fractional interpolator allows Ramp superimposed with FSK programmable fractional-N division. The INT and FRAC registers Ramp with 2 different sweep rates 25 define an overall N divider as N = INT + (FRAC/2 ). Ramp delay, frequency readback, and interrupt functions The ADF4169 can be used to implement frequency shift keying Programmable phase control (FSK) and phase shift keying (PSK) modulation. Frequency sweep 2.7 V to 3.45 V analog power supply modes are also available to generate various waveforms in the 1.8 V to 2 V digital power supply frequency domain, for example, sawtooth waveforms and Programmable charge pump currents triangular waveforms. Sweeps can be set to run automatically 3-wire serial interface or with each step manually triggered by an external pulse. The Digital lock detect ADF4169 features cycle slip reduction (CSR) circuitry, which ESD performance: 3000 V HBM, 1000 V CDM enables faster lock times without the need for modifications to Qualified for automotive applications the loop filter. APPLICATIONS Control of all on-chip registers is via a simple 3-wire interface. The FMCW radars ADF4169 operates with an analog power supply in the range of Communications test equipment 2.7 V to 3.45 V and a digital power supply in the range of 1.8 V Communications infrastructure to 2 V. The device can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AV DV SDV V R DD DD DD P SET ADF4169 SW2 REFERENCE 2 5-BIT REF IN DOUBLER R COUNTER 2 + PHASE DIVIDER CHARGE CP FREQUENCY PUMP DETECTOR CSR HIGH-Z DGND LOCK DETECT FAST LOCK SW1 SERIAL DATA OUTPUT SWITCH MUXOUT OUTPUT MUX DV DD R DIVIDER/2 + RF A IN N COUNTER N DIVIDER/2 RF B IN THIRD-ORDER CE FRACTIONAL TX INTERPOLATOR DATA CLK FRACTION MODULUS INTEGER 32-BIT 25 DATA VALUE 2 VALUE VALUE DATA LE REGISTER AGND DGND SDGND CPGND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12957-001ADF4169 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Step Register (R6) Map .............................................................. 23 Applications ....................................................................................... 1 Delay Register (R7) Map ........................................................... 24 General Description ......................................................................... 1 Applications Information .............................................................. 25 Functional Block Diagram .............................................................. 1 Initialization Sequence .............................................................. 25 Revision History ............................................................................... 2 RF Synthesizer Worked Example ............................................. 25 Specifications ..................................................................................... 3 Reference Doubler ...................................................................... 25 Timing Specifications .................................................................. 4 Cycle Slip Reduction for Faster Lock Times ........................... 25 Absolute Maximum Ratings ............................................................ 6 Modulation .................................................................................. 26 Thermal Resistance ...................................................................... 6 Waveform Generation ............................................................... 26 ESD Caution .................................................................................. 6 Waveform Deviations and Timing ........................................... 27 Pin Configuration and Function Descriptions ............................. 7 Single Ramp Burst ...................................................................... 27 Typical Performance Characteristics ............................................. 8 Single Triangular Burst .............................................................. 27 Theory of Operation ...................................................................... 10 Single Sawtooth Burst ................................................................ 27 Reference Input Section ............................................................. 10 Continuous Sawtooth Ramp ..................................................... 27 RF Input Stage ............................................................................. 10 Continuous Triangular Ramp ................................................... 27 RF INT Divider ........................................................................... 10 FMCW Radar Ramp Settings Worked Example ...................... 27 25-Bit Fixed Modulus ................................................................ 10 Activating the Ramp .................................................................. 28 INT, FRAC, and R Counter Relationship ................................ 10 Other Waveforms ....................................................................... 28 R Counter .................................................................................... 10 Ramp Complete Signal to MUXOUT ..................................... 31 Phase Frequency Detector and Charge Pump ........................... 11 External Control of Ramp Steps ............................................... 31 MUXOUT and Lock Detect ...................................................... 11 Interrupt Modes and Frequency Readback ............................ 31 Input Shift Register..................................................................... 11 Fast Lock Mode .......................................................................... 33 Program Modes .......................................................................... 11 Spur Mechanisms ....................................................................... 33 Register Maps .................................................................................. 12 Filter Design Using ADIsimPLL ............................................... 34 FRAC/INT Register (R0) Map .................................................. 14 PCB Design Guidelines for the Chip Scale Package .............. 34 LSB FRAC Register (R1) Map ................................................... 15 Application of the ADF4169 in FMCW Radar ...................... 35 R Divider Register (R2) Map .................................................... 16 Outline Dimensions ....................................................................... 36 Function Register (R3) Map ...................................................... 18 Ordering Guide .......................................................................... 36 Clock Register (R4) Map ........................................................... 20 Automotive Products ................................................................. 36 Deviation Register (R5) Map .................................................... 22 REVISION HISTORY 7/15Revision 0: Initial Version Rev. 0 Page 2 of 36