Low Phase Noise, Fast Settling PLL Frequency Synthesizer Data Sheet ADF4193 FEATURES GENERAL DESCRIPTION New, fast settling, fractional-N PLL architecture The ADF4193 frequency synthesizer can be used to implement Single PLL replaces ping-pong synthesizers local oscillators in the upconversion and downconversion Frequency hop across GSM band in 5 s with phase settled sections of wireless receivers and transmitters. Its architecture by 20 s is specifically designed to meet the GSM/EDGE lock time 0.5 rms phase error at 2 GHz RF output requirements for base stations. It consists of a low noise, digital Digitally programmable output phase phase frequency detector (PFD), and a precision differential RF input range up to 3.5 GHz charge pump. There is also a differential amplifier to convert 3-wire serial interface the differential charge pump output to a single-ended voltage On-chip, low noise differential amplifier for the external voltage-controlled oscillator (VCO). Phase noise figure of merit: 216 dBc/Hz The - based fractional interpolator, working with the N Loop filter design possible using ADIsimPLL divider, allows programmable modulus fractional-N division. Qualified for automotive applications Additionally, the 4-bit reference (R) counter and on-chip APPLICATIONS frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop GSM/EDGE base stations (PLL) can be implemented if the synthesizer is used with an PHS base stations external loop filter and a VCO. The switching architecture Instrumentation and test equipment ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures. FUNCTIONAL BLOCK DIAGRAM SDV DV 1 DV 2 DV 3 AV 1 V 1 V 2 V 3 R DD DD DD DD DD P P P SET REFERENCE SW1 4-BIT R 2 + PHASE 2 DIVIDER COUNTER CP REF + CHARGE OUT+ IN FREQUENCY DOUBLER PUMP CP DETECTOR OUT SW2 V DD HIGH Z DGND CMR LOCK DETECT DIFFERENTIAL AMPLIFIER AIN OUTPUT MUX MUX OUT R DIV + AIN+ N DIV A OUT N COUNTER SW3 FRACTIONAL INTERPOLATOR RF IN+ CLK 24-BIT RF DATA IN DATA REGISTER FRACTION MODULUS INTEGER LE REG REG REG ADF4193 A 1 A 2 D 1 D 2 D 3 SD SW GND GND GND GND GND GND GND Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052015 Analog Devices, Inc. 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Technical Support www.analog.com 05328-001ADF4193 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register (R3) .............................................................. 19 Applications ....................................................................................... 1 Charge Pump Register (R4) ...................................................... 20 General Description ......................................................................... 1 Power-Down Register (R5) ....................................................... 21 Functional Block Diagram .............................................................. 1 Mux Register (R6) ...................................................................... 22 Revision History ............................................................................... 3 Programming .................................................................................. 23 Specifications ..................................................................................... 4 Worked Example ........................................................................ 23 Timing Characteristics ................................................................ 5 Spur Mechanisms ....................................................................... 23 Absolute Maximum Ratings ............................................................ 6 Power-Up Initialization ............................................................. 24 ESD Caution .................................................................................. 6 Changing the Frequency of the PLL and the Phase Look-Up Table ............................................................................................. 24 Pin Configuration and Function Descriptions ............................. 7 Applications Information .............................................................. 26 Typical Performance Characteristics ............................................. 9 Local Oscillator for A GSM Base Station ................................ 26 Theory of Operation ...................................................................... 12 Interfacing ................................................................................... 28 Reference Input Section ............................................................. 12 PCB Design Guidelines for Chip Scale Package .................... 28 RF Input Stage ............................................................................. 12 Outline Dimensions ....................................................................... 29 Register Map .................................................................................... 15 Ordering Guide .......................................................................... 29 FRAC/INT Register (R0) ........................................................... 16 Automotive Products ................................................................. 29 MOD/R Register (R1) ................................................................ 17 Phase Register (R2) .................................................................... 18 Rev. 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