Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer Data Sheet ADF4196 FEATURES GENERAL DESCRIPTION Fast settling, fractional-N PLL architecture The ADF4196 frequency synthesizer can be used to implement Single PLL replaces ping-pong synthesizers local oscillators (LO) in the upconversion and downconversion Frequency hop across GSM band in 5 s with phase settled sections of wireless receivers and transmitters. Its architecture is within 20 s specifically designed to meet the GSM/EDGE lock time require- 1 degree rms phase error at 4 GHz RF output ments for base stations, and the fast settling feature makes the Digitally programmable output phase ADF4196 suitable for pulse Doppler radar applications. RF input range up to 6 GHz The ADF4196 consists of a low noise, digital phase frequency 3-wire serial interface detector (PFD) and a precision differential charge pump. On-chip, low noise differential amplifier A differential amplifier converts the differential charge pump Phase noise figure of merit: 216 dBc/Hz output to a single-ended voltage for the external voltage controlled APPLICATIONS oscillator (VCO). The sigma-delta (-) based fractional inter- polator, working with the N divider, allows programmable modulus GSM/EDGE base stations fractional-N division. Additionally, the 4-bit reference (R) counter PHS base stations and on-chip frequency doubler allow selectable reference signal Pulse Doppler radar (REF ) frequencies at the PFD input. IN Instrumentation and test equipment Beam-forming/phased array systems A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures. FUNCTIONAL BLOCK DIAGRAM SDV DV 1 DV 2 DV 3 AV V 1 V 2 V 3 R DD DD DD DD DD P P P SET REFERENCE SW1 4-BIT R /2 + PHASE 2 DIVIDER COUNTER REF + CP CHARGE OUT+ IN FREQUENCY DOUBLER PUMP CP DETECTOR OUT SW2 V DD HIGH-Z DGND CMR LOCK DETECT DIFFERENTIAL AMPLIFIER AIN OUTPUT MUX MUX OUT R DIV + AIN+ N DIV A OUT N COUNTER SW3 FRACTIONAL INTERPOLATOR RF IN+ CLK 24-BIT RF DATA IN DATA REGISTER FRACTION MODULUS INTEGER LE REG REG REG ADF4196 A 1 A 2 D 1 D 2 D 3 SD SW GND GND GND GND GND GND GND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. 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Technical Support www.analog.com 09450-001ADF4196 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 13 Applications ....................................................................................... 1 Register Map ................................................................................... 14 General Description ......................................................................... 1 FRAC/INT Register (R0) Latch Map ....................................... 15 Functional Block Diagram .............................................................. 1 MOD/R Register (R1) Latch Map ............................................ 16 Revision History ............................................................................... 2 Phase Register (R2) Bit Latch Map .......................................... 17 Specif icat ions ..................................................................................... 3 Function Register (R3) Latch Map ........................................... 18 Timing Characteristics ................................................................ 4 Charge Pump Register (R4) Latch Map .................................. 19 Absolute Maximum Ratings ............................................................ 5 Power-Down Register (R5) Bit Map ........................................ 20 Thermal Resistance ...................................................................... 5 Mux Register (R6) Latch Map and Truth Table ..................... 21 Transistor Count ........................................................................... 5 Programming the ADF4196 .......................................................... 22 ESD Caution .................................................................................. 5 Worked Example ........................................................................ 22 Pin Configuration and Function Descriptions ............................. 6 Spur Mechanisms ....................................................................... 22 Typical Performance Characteristics ............................................. 8 Power-Up Initialization ............................................................. 23 Theory of Operation ...................................................................... 11 Changing the Frequency of the PLL and the Phase Lookup Table ............................................................................................. 23 General Description ................................................................... 11 Applications Information .............................................................. 25 Reference Input ........................................................................... 11 Local Oscillator for a GSM Base Station ................................. 25 RF Input Stage ............................................................................. 11 Interfacing ................................................................................... 27 PFD and Charge Pump .............................................................. 12 PCB Design Guidelines ............................................................. 27 Differential Charge Pump ......................................................... 12 Outline Dimensions ....................................................................... 28 Fast Lock Timeout Counters ..................................................... 12 Ordering Guide .......................................................................... 28 Differential Amplifier ................................................................ 13 MUX and Lock Detect ......................................................... 13 OUT REVISION HISTORY 5/15Rev. C to Rev. D Changed LFCSP VQ to LFCSP WQ ......................... Throughout Changes to Figure 3 .......................................................................... 6 Changed ADuC70xx Interface Section to Analog Microcontroller Interface Section ................................................ 27 Changes to Analog Microcontroller Interface Section and Figure 38 .......................................................................................... 27 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 1/13Rev. B to Rev. C Change to Power-Up Initialization Section ................................ 23 Changes to Ordering Guide .......................................................... 28 12/11Rev. A to Rev. B Changes to Figure 10, Figure 11, Figure 13, and Figure 14 ............................................................................................ 9 Change to Figure 31 ....................................................................... 17 10/11Revision A: Initial Version Rev. D Page 2 of 28