Dual Fractional-N/Integer-N Frequency Synthesizer Data Sheet ADF4252 FEATURES GENERAL DESCRIPTION 3.0 GHz fractional-N/1.2 GHz integer-N The ADF4252 is a dual fractional-N/integer-N frequency 2.7 V to 3.3 V power supply synthesizer that can be used to implement local oscillators (LO) Separate V allows extended tuning voltage to 5 V P in the upconversion and downconversion sections of wireless Programmable dual modulus prescaler receivers and transmitters. Both the RF and IF synthesizers RF: 4/5, 8/9 consist of a low noise digital phase frequency detector (PFD), a IF: 8/9, 16/17, 32/33, 64/65 precision charge pump, and a programmable reference divider. Programmable charge pump currents The RF synthesizer has a --based fractional interpolator that 3-wire serial interface allows programmable fractional-N division. The IF synthesizer Digital lock detect has programmable integer-N counters. A complete phase-locked Power-down mode loop (PLL) can be implemented if the synthesizer is used with Programmable modulus on fractional-N synthesizer an external loop filter and voltage controlled oscillator (VCO). Trade off noise vs. spurious performance Control of all the on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to APPLICATIONS 3.3 V and can be powered down when not in use. Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment FUNCTIONAL BLOCK DIAGRAM V 1 V 2 V 3 DV V 1 V 2 R DD DD DD DD P P SET ADF4252 REFERENCE 4-BIT R COUNTER PHASE 2 CHARGE REF FREQUENCY CP IN RF DOUBLER PUMP DETECTOR REF OUT LOCK OUTPUT MUXOUT MUX DETECT RF A IN FRACTIONAL-N RF DIVIDER RF B IN CLK 24-BIT DATA DATA REGISTER LE IF B IN INTEGER-N IF DIVIDER IF A IN PHASE CHARGE FREQUENCY CP IF PUMP DETECTOR 15-BIT R COUNTER 2 DOUBLER A 1 A 2 D CP 1 CP 2 GND GND GND GND GND Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20022019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 02946-001ADF4252 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RF N Divider Register (Address R0) ....................................... 23 Applications ....................................................................................... 1 RF R Divider Register (Address R1) ........................................ 23 General Description ......................................................................... 1 RF Control Register (Address R2) ........................................... 23 Functional Block Diagram .............................................................. 1 Master Register (Address R3) ................................................... 24 Revision History ............................................................................... 3 IF N Divider Register (Address R4) ......................................... 24 Specif icat ions ..................................................................................... 4 IF R Divider Register (Address R5) ......................................... 25 Timing Characteristics ................................................................ 5 IF Control Register (Address R6) ............................................. 25 Absolute Maximum Ratings ............................................................ 6 Device Programming after Initial Power-Up.............................. 26 ESD Caution .................................................................................. 6 RF and IF Synthesizers Operational ........................................ 26 Pin Configuration and Function Descriptions ............................. 7 RF Synthesizer Operational, IF Power-Down .......................... 26 Typical Performance Characteristics ............................................. 8 IF Synthesizer Operational, RF Power-Down .......................... 26 Detailed Functional Block Diagram ............................................ 12 RF Synthesizer: An Example ..................................................... 26 Theory of Operation ...................................................................... 13 IF Synthesizer: An Example ...................................................... 26 Reference Input Section ............................................................. 13 Modulus ....................................................................................... 26 RF and IF Input Stage ................................................................ 13 Reference Doubler and Reference Divider ............................. 26 RF INT Divider ........................................................................... 13 12-Bit Programmable Modulus ................................................ 26 INT, FRAC, MOD, and R Relationship ................................... 13 Spurious Optimization and Fastlock ....................................... 27 RF R Counter .............................................................................. 13 Spurious SignalsPredicting Where They Appear ............... 27 IF R Counter ............................................................................... 13 Pres caler ....................................................................................... 27 IF Prescaler (P/P + 1) ................................................................. 14 Filter DesignADIsimPLL ....................................................... 27 IF A and B Counters .................................................................. 14 Interfacing ....................................................................................... 28 Pulse Swallow Function ............................................................. 14 ADuC812 Interface .................................................................... 28 Phase Frequency Detector (PFD) and Charge Pump ............ 14 ADSP-2181 Interface ................................................................. 28 MUXOUT and Lock Detect ...................................................... 14 PCB Design Guidelines for Chip Scale Package ......................... 29 Lock Detect ................................................................................. 14 Outline Dimensions ....................................................................... 30 Input Shift Register..................................................................... 14 Ordering Guide .......................................................................... 30 Register Maps .................................................................................. 15 Register Descriptions ..................................................................... 23 Rev. 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