Wideband Synthesizer with Integrated VCO Data Sheet ADF4350 FEATURES GENERAL DESCRIPTION Output frequency range: 137.5 MHz to 4400 MHz The ADF4350 allows implementation of fractional-N or Fractional-N synthesizer and integer-N synthesizer integer-N phase-locked loop (PLL) frequency synthesizers Low phase noise VCO if used with an external loop filter and external reference Programmable divide-by-1/-2/-4/-8/-16 output frequency. Typical rms jitter: <0.4 ps rms The ADF4350 has an integrated voltage controlled oscillator Power supply: 3.0 V to 3.6 V (VCO) with a fundamental output frequency ranging from Logic compatibility: 1.8 V 2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16 Programmable dual-modulus prescaler of 4/5 or 8/9 circuits allow the user to generate RF output frequencies as low Programmable output power level as 137.5 MHz. For applications that require isolation, the RF RF output mute function output stage can be muted. The mute function is both pin- and 3-wire serial interface software-controllable. An auxiliary RF output is also available, Analog and digital lock detect which can be powered down if not in use. Switched bandwidth fast-lock mode Control of all the on-chip registers is through a simple 3-wire Cycle slip reduction interface. The device operates with a power supply ranging APPLICATIONS from 3.0 V to 3.6 V and can be powered down when not in use. Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation FUNCTIONAL BLOCK DIAGRAM SDV AV DV V R V DD DD DD P SET VCO MULTIPLEXER MUXOUT 10-BIT R 2 2 COUNTER DIVIDER REF IN DOUBLER LOCK DETECT SW FL SWITCH O LD CLK DATA DATA REGISTER FUNCTION CHARGE CP OUT LE LATCH PUMP PHASE COMPARATOR V TUNE V REF VCO V COM CORE TEMP INTEGER FRACTION MODULUS REG REG REG RF A+ OUT OUTPUT THIRD-ORDER 1/2/4/8/16 FRACTIONAL STAGE RF A OUT INTERPOLATOR PDBRF OUTPUT RF B+ OUT N COUNTER STAGE RF B OUT MULTIPLEXER ADF4350 CE AGND DGND CP SD A GND GND GNDVCO Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com MULTIPLEXER 07325-001ADF4350 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 1 ..................................................................................... 18 Applications ....................................................................................... 1 Register 2 ..................................................................................... 18 General Description ......................................................................... 1 Register 3 ..................................................................................... 20 Functional Block Diagram .............................................................. 1 Register 4 ..................................................................................... 20 Revision History ............................................................................... 2 Register 5 ..................................................................................... 20 Specif icat ions ..................................................................................... 3 Initialization Sequence .............................................................. 21 Timing Characteristics ................................................................ 5 RF SynthesizerA Worked Example ...................................... 21 Absolute Maximum Ratings ............................................................ 6 Modulus ....................................................................................... 21 Transistor Count ........................................................................... 6 Reference Doubler and Reference Divider ............................. 21 ESD Caution .................................................................................. 6 12-Bit Programmable Modulus ................................................ 21 Pin Configuration and Function Descriptions ............................. 7 Cycle Slip Reduction for Faster Lock Times ........................... 22 Typical Performance Characteristics ............................................. 9 Spurious Optimization and Fast lock ...................................... 22 Circuit Description ......................................................................... 11 Fast-Lock Timer and Register Sequences ............................... 22 Reference Input Section ............................................................. 11 Fast LockAn Example ............................................................ 22 RF N Divider ............................................................................... 11 Fast LockLoop Filter Topology ............................................. 23 INT, FRAC, MOD, and R Counter Relationship .................... 11 Spur Mechanisms ....................................................................... 23 INT N MODE ............................................................................. 11 Spur Consistency and Fractional Spur Optimization ........... 24 R Counter .................................................................................... 11 Phase Resync ............................................................................... 24 Phase Frequency Detector (PFD) and Charge Pump ............ 11 Applications Information .............................................................. 25 MUXOUT and LOCK Detect ................................................... 12 Direct Conversion Modulator .................................................. 25 Input Shift Registers ................................................................... 12 Interfacing ................................................................................... 26 Program Modes .......................................................................... 12 PCB Design Guidelines for a Chip Scale Package ................. 26 VCO.............................................................................................. 12 Output Matching ........................................................................ 27 Output Stage ................................................................................ 13 Outline Dimensions ....................................................................... 31 Register Maps .................................................................................. 14 Ordering Guide .......................................................................... 31 Register 0 ..................................................................................... 18 REVISION HISTORY 5/16Rev. A to Rev. B 4/11Rev. 0 to Rev. A Changes to Figure 3 .......................................................................... 7 Changes to Typical rms Jitter in Features Section ......................... 1 Changes to the ADuC7019 to ADuC7029 Family Interface Changes to Specifications ................................................................. 3 Section, Figure 35, and Figure 35 Caption .................................. 26 Changes Output Stage Section ...................................................... 13 Updated Outline Dimensions ....................................................... 30 Changes to Figure 29 ...................................................................... 17 Changes to Ordering Guide .......................................................... 30 Changes to Fast LockAn Example Section ............................. 22 Changes to Direct Conversion Modulator Section and Figure 34 ......................................................................................... 25 Changes to ADuC70xx Interface Section and ADSP-BF527 Interface Section ............................................................................. 26 Changes to Output Matching Section and Table 7 .................... 27 Added Table 8 ................................................................................. 28 Changes to Ordering Guide .......................................................... 29 11/08Revision 0: Initial Version Rev. B Page 2 of 34