Wideband Synthesizer with Integrated VCO Data Sheet ADF4351 FEATURES GENERAL DESCRIPTION Output frequency range: 35 MHz to 4400 MHz The ADF4351 allows implementation of fractional-N or integer-N Fractional-N synthesizer and integer-N synthesizer phase-locked loop (PLL) frequency synthesizers when used with Low phase noise VCO an external loop filter and external reference frequency. Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output The ADF4351 has an integrated voltage controlled oscillator (VCO) Typical jitter: 0.3 ps rms with a fundamental output frequency ranging from 2200 MHz to Typical EVM at 2.1 GHz: 0.4% 4400 MHz. In addition, divide-by-1/-2/-4/-8/-16/-32/-64 circuits Power supply: 3.0 V to 3.6 V allow the user to generate RF output frequencies as low as 35 MHz. Logic compatibility: 1.8 V For applications that require isolation, the RF output stage can be Programmable dual-modulus prescaler of 4/5 or 8/9 muted. The mute function is both pin- and software-controllable. Programmable output power level An auxiliary RF output is also available, which can be powered RF output mute function down when not in use. 3-wire serial interface Control of all on-chip registers is through a simple 3-wire interface. Analog and digital lock detect The device operates with a power supply ranging from 3.0 V to Switched bandwidth fast lock mode 3.6 V and can be powered down when not in use. Cycle slip reduction APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation FUNCTIONAL BLOCK DIAGRAM SDV AV DV V R V DD DD DD P SET VCO MULTIPLEXER MUXOUT 10-BIT R 2 2 COUNTER DIVIDER REF IN DOUBLER LOCK FAST LOCK DETECT SW SWITCH LD CLK DATA DATA REGISTER FUNCTION CHARGE CP LATCH LE PUMP OUT PHASE COMPARATOR V TUNE V REF V COM VCO CORE TEMP INTEGER FRACTION MODULUS VALUE VALUE VALUE RF A+ OUT OUTPUT THIRD-ORDER 1/2/4/8/16/ STAGE FRACTIONAL 32/64 RF A OUT INTERPOLATOR PDB RF RF B+ OUTPUT OUT N COUNTER STAGE RF B OUT MULTIPLEXER ADF4351 AGND DGND CP SD A CE GND GND GNDVCO Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com MULTIPLEXER 09800-001ADF4351 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 1 ..................................................................................... 18 Applications ....................................................................................... 1 Register 2 ..................................................................................... 18 General Description ......................................................................... 1 Register 3 ..................................................................................... 19 Functional Block Diagram .............................................................. 1 Register 4 ..................................................................................... 20 Revision History ............................................................................... 2 Register 5 ..................................................................................... 20 Specifications ..................................................................................... 3 Register Initialization Sequence ............................................... 20 Timing Characteristics ................................................................ 5 RF SynthesizerA Worked Example ...................................... 21 Absolute Maximum Ratings ............................................................ 6 Reference Doubler and Reference Divider ............................. 21 Transistor Count ........................................................................... 6 12-Bit Programmable Modulus ................................................ 21 Thermal Resistance ...................................................................... 6 Cycle Slip Reduction for Faster Lock Times ........................... 22 ESD Caution .................................................................................. 6 Spurious Optimization and Fast Lock ..................................... 22 Pin Configuration and Function Descriptions ............................. 7 Fast Lock Timer and Register Sequences ................................ 22 Typical Performance Characteristics ............................................. 9 Fast Lock Example ..................................................................... 22 Circuit Description ......................................................................... 11 Fast Lock Loop Filter Topology ................................................ 23 Reference Input Section ............................................................. 11 Spur Mechanisms ....................................................................... 23 RF N Divider ............................................................................... 11 Spur Consistency and Fractional Spur Optimization ........... 24 Phase Frequency Detector (PFD) and Charge Pump ............ 11 Phase Resync ............................................................................... 24 MUXOUT and Lock Detect ...................................................... 12 Applications Information .............................................................. 25 Input Shift Registers ................................................................... 12 Direct Conversion Modulator .................................................. 25 Program Modes .......................................................................... 12 Interfacing to the ADuC70xx and the ADSP-BF527 ............. 26 VCO.............................................................................................. 12 PCB Design Guidelines for a Chip Scale Package ................. 26 Output Stage ................................................................................ 13 Output Matching ........................................................................ 27 Register Maps .................................................................................. 14 Outline Dimensions ....................................................................... 28 Register 0 ..................................................................................... 18 Ordering Guide .......................................................................... 28 REVISION HISTORY 1/2017Rev. 0 to Rev. A Changed CP-32-2 to CP-32-7 ...................................... Throughout Change to Figure 3 ........................................................................... 7 Updated Outline Dimension ......................................................... 28 Changes to Ordering Guide .......................................................... 28 5/2012Revision 0: Initial Version Rev. A Page 2 of 28