Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF4355-2 FEATURES GENERAL DESCRIPTION RF output frequency range: 54 MHz to 4400 MHz The ADF4355-2 allows implementation of fractional-N or Fractional-N synthesizer and integer-N synthesizer integer-N phase-locked loop (PLL) frequency synthesizers High resolution 38-bit modulus when used with an external loop filter and an external reference Low phase noise, VCO frequency. A series of frequency dividers permits operation Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output from 54 MHz to 4400 MHz. Analog and digital power supplies: 3.3 V The ADF4355-2 has an integrated voltage controlled oscillator Charge pump and VCO power supplies: 5 V typical (VCO) with a fundamental output frequency ranging from Logic compatibility: 1.8 V 3400 MHz to 6800 MHz. In addition, the VCO frequency is Programmable dual modulus prescaler of 4/5 or 8/9 connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow Programmable output power level the user to generate radio frequency (RF) output frequencies as RF output mute function low as 54 MHz. For applications that require isolation, the RF 3-wire serial interface output stage can be muted. The mute function is both pin and Analog and digital lock detect software controllable. APPLICATIONS Control of all on-chip registers is through a simple 3-wire interface. Wireless infrastructure (W-CDMA, TD-SCDMA, The ADF4355-2 operates with analog and digital power supplies, WiMAX, GSM, PCS, DCS, DECT) ranging from 3.15 V to 3.45 V, with charge pump and VCO Point to point/point to multipoint microwave links supplies from 4.75 V to 5.25 V. The ADF4355-2 also contains Satellites/VSATs hardware and software power-down modes. Test equipment/instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM AV DV V R V CE DD DD P SET VCO V AV RF DD MULTIPLEXER MUXOUT 10-BIT R 2 REF A IN 2 COUNTER DIVIDER DOUBLER LOCK REF B C 1 IN REG DETECT C 2 REG CLK DATA DATA REGISTER FUNCTION CHARGE CP OUT LE LATCH PUMP PHASE COMPARATOR V TUNE V REF V VCO BIAS CORE INTEGER FRACTION MODULUS V REGVCO REG REG REG RF A+ OUT 1/2/4/8 OUTPUT THIRD-ORDER 16/32/64 FRACTIONAL STAGE RF A OUT INTERPOLATOR PDB RF RF B+ OUTPUT OUT N COUNTER STAGE RF B OUT MULTIPLEXER ADF4355-2 A CP SD A GND GND A GND GNDVCO GNDRF Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12452-001ADF4355-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 4 ..................................................................................... 23 Applications ....................................................................................... 1 Register 5 ..................................................................................... 24 General Description ......................................................................... 1 Register 6 ..................................................................................... 25 Functional Block Diagram .............................................................. 1 Register 7 ..................................................................................... 27 Revision History ............................................................................... 3 Register 8 ..................................................................................... 28 Specifications ..................................................................................... 4 Register 9 ..................................................................................... 28 Timing Characteristics ................................................................ 6 Register 10 ................................................................................... 29 Absolute Maximum Ratings ............................................................ 7 Register 11 ................................................................................... 29 Transistor Count ........................................................................... 7 Register 12 ................................................................................... 30 ESD Caution .................................................................................. 7 Register Initialization Sequence ............................................... 30 Pin Configuration and Function Descriptions ............................. 8 Frequency Update Sequence ..................................................... 31 Typical Performance Characteristics ........................................... 10 RF SynthesizerA Worked Example ...................................... 31 Circuit Description ......................................................................... 13 Reference Doubler and Reference Divider ............................. 32 Reference Input Section ............................................................. 13 Spurious Optimization and Fast Lock ..................................... 32 RF N Divider ............................................................................... 13 Optimizing Jitter ......................................................................... 32 Phase Frequency Detector (PFD) and Charge Pump ............ 14 Spur Mechanisms ....................................................................... 32 MUXOUT and Lock Detect ...................................................... 14 Lock Time.................................................................................... 32 Input Shift Registers ................................................................... 14 Applications Information .............................................................. 34 Program Modes .......................................................................... 15 Direct Conversion Modulator .................................................. 34 VCO.............................................................................................. 15 Printed Circuit Board (PCB) Design Guidelines for a Chip- Scale Package .............................................................................. 35 Output Stage ................................................................................ 15 Output Matching ........................................................................ 36 Register Maps .................................................................................. 17 Outline Dimensions ....................................................................... 37 Register 0 ..................................................................................... 19 Ordering Guide .......................................................................... 37 Register 1 ..................................................................................... 20 Register 2 ..................................................................................... 21 Register 3 ..................................................................................... 22 Rev. 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