Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF4355-3 FEATURES GENERAL DESCRIPTION RF output frequency range: 51.5625 MHz to 6600 MHz The ADF4355-3 allows the implementation of fractional-N or Fractional-N synthesizer and integer-N synthesizer integer-N phase-locked loop (PLL) frequency synthesizers when High resolution 38-bit modulus used with an external loop filter and an external reference Low phase noise, voltage controlled oscillator (VCO) frequency. A series of frequency dividers at the output provide Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output operation from 51.5625 MHz to 6600 MHz. All power supplies: 3.3 V The ADF4355-3 has an integrated VCO with a fundamental Logic compatibility: 1.8 V output frequency ranging from 3300 MHz to 6600 MHz. In Programmable dual modulus prescaler of 4/5 or 8/9 addition, the VCO frequency is connected to divide by 1, 2, 4, 8, Programmable output power level 16, 32, or 64 circuits that allow the user to generate RF output RF output mute function frequencies as low as 51.5625 MHz. For applications that require 3-wire serial interface isolation, the RF output stage can be muted. The mute function Analog and digital lock detect is both pin- and software-controllable. APPLICATIONS Control of all on-chip registers is through a simple 3-wire interface. Wireless infrastructure (W-CDMA, TD-SCDMA, The ADF4355-3 operates with analog, digital, charge pump, and WiMAX, GSM, PCS, DCS, DECT) VCO power supplies ranging from 3.1515 V to 3.4485 V. The Point to point/point to multipoint microwave links ADF4355-3 also contains hardware and software power-down Satellites/VSATs modes. Test equipment/instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM AV DV V R V CE DD DD P SET VCO V AV RF DD MULTIPLEXER MUXOUT 10-BIT R 2 REF A IN 2 COUNTER DIVIDER DOUBLER LOCK REF B IN C 1 REG DETECT C 2 REG CLK DATA DATA REGISTER FUNCTION CHARGE CP OUT LE LATCH PUMP PHASE COMPARATOR V TUNE V REF VCO V BIAS CORE INTEGER FRACTION MODULUS V REGVCO REG REG REG RF A+ OUT 1/2/4/8 OUTPUT THIRD-ORDER 16/32/64 STAGE FRACTIONAL RF A OUT INTERPOLATOR PDB RF N COUNTER RF B+ OUTPUT OUT STAGE RF B OUT MULTIPLEXER ADF4355-3 A CP SD A A GND GND GNDRF GND GNDVCO Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com 13345-001ADF4355-3 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 4 ..................................................................................... 22 Applications ....................................................................................... 1 Register 5 ..................................................................................... 23 General Description ......................................................................... 1 Register 6 ..................................................................................... 24 Functional Block Diagram .............................................................. 1 Register 7 ..................................................................................... 26 Revision History ............................................................................... 2 Register 8 ..................................................................................... 27 Specifications ..................................................................................... 3 Register 9 ..................................................................................... 27 Timing Characteristics ................................................................ 5 Register 10 ................................................................................... 28 Absolute Maximum Ratings ............................................................ 6 Register 11 ................................................................................... 28 Transistor Count ........................................................................... 6 Register 12 ................................................................................... 29 ESD Caution .................................................................................. 6 Register Initialization Sequence ............................................... 29 Pin Configuration and Function Descriptions ............................. 7 Frequency Update Sequence ..................................................... 30 Typical Performance Characteristics ............................................. 9 RF SynthesizerA Worked Example ...................................... 30 Theory of Operation ...................................................................... 12 Reference Doubler and Reference Divider ............................. 30 Reference Input Section ............................................................. 12 Spurious Optimization and Fast Lock ..................................... 31 RF N Divider ............................................................................... 12 Optimizing Jitter ......................................................................... 31 Phase Frequency Detector (PFD) and Charge Pump ............ 13 Spur Mechanisms ....................................................................... 31 MUXOUT and Lock Detect ...................................................... 13 Lock Time.................................................................................... 31 Input Shift Registers ................................................................... 13 Applications Information .............................................................. 32 Program Modes .......................................................................... 14 Direct Conversion Modulator .................................................. 32 VCO.............................................................................................. 14 Power Supplies ............................................................................ 33 Output Stage ................................................................................ 14 Printed Circuit Board (PCB) Design Guidelines for a Chip- Scale Package .............................................................................. 33 Loop Filter ................................................................................... 14 Output Matching ........................................................................ 33 Register Maps .................................................................................. 16 Outline Dimensions ....................................................................... 34 Register 0 ..................................................................................... 18 Ordering Guide .......................................................................... 34 Register 1 ..................................................................................... 19 Register 2 ..................................................................................... 20 Register 3 ..................................................................................... 21 REVISION HISTORY 8/2017Rev. A to Rev. B Changes to Figure 25 ...................................................................... 17 Changes to Frequency Update Sequence .................................... 30 Changes to Reference Mode Section ........................................... 23 Updated Outline Dimensions ....................................................... 34 Changes to Negative Bleed Section .............................................. 24 Changes to Ordering Guide .......................................................... 34 Changes to Charge Pump Bleed Current Section ...................... 25 Changes to Figure 34, Figure 35, and Register 8 Section .......... 27 1/2016Rev. 0 to Rev. A Changes to Figure 37 and Register 11 Section ........................... 28 Change to Integrated RMS Jitter Parameter, Unit Column, Table 1 ................................................................................................ 4 7/2015Revision 0: Initial Version Changes to Reference Input Section ............................................ 12 Changes to Table 6 .......................................................................... 15 Rev. B Page 2 of 34