6.8 GHz Wideband Synthesizer with Integrated VCO Data Sheet ADF4356 FEATURES GENERAL DESCRIPTION RF output frequency range: 53.125 MHz to 6800 MHz The ADF4356 allows implementation of fractional-N or integer-N Integer channel: 227 dBc/Hz phase-locked loop (PLL) frequency synthesizers when used with Fractional channel: 225 dBc/Hz an external loop filter and an external reference frequency. A series Integrated RMS jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output of frequency dividers at another frequency output permits Fractional-N synthesizer and integer-N synthesizer operation from 53.125 MHz to 6800 MHz. Pin compatible to the ADF4355 The ADF4356 has an integrated VCO with a fundamental High resolution, 52-bit modulus output frequency ranging from 3400 MHz to 6800 MHz. In Phase frequency detector (PFD) operation to 125 MHz addition, the VCO frequency is connected to divide by 1, 2, 4, 8, Reference input frequency operation to 600 MHz 16, 32, or 64 circuits that allow the user to generate RF output Maintains frequency lock over 40C to +85C frequencies as low as 53.125 MHz. For applications that require Low phase noise, voltage controlled oscillator (VCO) isolation, the RF output stage can be muted. The mute function Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output is both pin- and software-controllable. Analog and digital power supplies: 3.3 V Control of all on-chip registers is through a simple 3-wire interface. Charge pump and VCO power supplies: 5.0 V typical The ADF4356 operates with analog and digital power supplies Logic compatibility: 1.8 V ranging from 3.15 V to 3.45 V, with charge pump and VCO Programmable output power level supplies from 4.75 V to 5.25 V. The ADF4356 also contains RF output mute function hardware and software power-down modes. Supported in the ADIsimPLL design tool APPLICATIONS Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM CE DV AV DV V V V DD DD DD P VCO RF MULTIPLEXER MUXOUT 10-BIT R 2 REF A 2 COUNTER DIVIDER IN DOUBLER LOCK REF B IN DETECT C REG1 C REG2 CLK DATA DATA REGISTER FUNCTION CHARGE CP LATCH OUT LE PUMP PHASE COMPARATOR V TUNE V REF V VCO BIAS CORE V REGVCO INTEGER FRACTION MODULUS VALUE VALUE VALUE RF A+ OUT OUTPUT THIRD-ORDER 1/2/4/8/16/ STAGE FRACTIONAL 32/64 RF A OUT INTERPOLATOR PDB RF RF B+ OUTPUT OUT N COUNTER STAGE RF B OUT MULTIPLEXER ADF4356 A SD CP A A GND GND GND GNDRF GNDVCO Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com MULTIPLEXER 15084-001ADF4356 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 4 ..................................................................................... 21 Applications ....................................................................................... 1 Register 5 ..................................................................................... 22 General Description ......................................................................... 1 Register 6 ..................................................................................... 23 Functional Block Diagram .............................................................. 1 Register 7 ..................................................................................... 25 Revision History ............................................................................... 2 Register 8 ..................................................................................... 26 Specifications ..................................................................................... 3 Register 9 ..................................................................................... 26 Timing Characteristics ................................................................ 5 Register 10 ................................................................................... 27 Absolute Maximum Ratings ............................................................ 6 Register 11 ................................................................................... 28 Transistor Count ........................................................................... 6 Register 12 ................................................................................... 28 ESD Caution .................................................................................. 6 Register 13 ................................................................................... 29 Pin Configuration and Function Descriptions ............................. 7 Register Initialization Sequence ............................................... 29 Typical Performance Characteristics ............................................. 9 Frequency Update Sequence ..................................................... 30 Theory of Operation ...................................................................... 12 RF SynthesizerA Worked Example ...................................... 30 Reference Input Section ............................................................. 12 Reference Doubler and Reference Divider ............................. 31 RF N Divider ............................................................................... 12 Spurious Optimization and Fast Lock ..................................... 31 Phase Frequency Detector (PFD) and Charge Pump ............ 13 Optimizing Jitter ......................................................................... 31 MUXOUT and Lock Detect ...................................................... 13 Spur Mechanisms ....................................................................... 31 Input Shift Registers ................................................................... 13 Lock Time.................................................................................... 31 Program Modes .......................................................................... 14 Applications Information .............................................................. 33 VCO.............................................................................................. 14 Power Supplies ............................................................................ 33 Output Stage ................................................................................ 14 Printed Circuit Board (PCB) Design Guidelines for a Chip- Scale Package .............................................................................. 33 Register Maps .................................................................................. 16 Output Matching ........................................................................ 34 Register 0 ..................................................................................... 18 Outline Dimensions ....................................................................... 35 Register 1 ..................................................................................... 19 Ordering Guide .......................................................................... 35 Register 2 ..................................................................................... 19 Register 3 ..................................................................................... 20 REVISION HISTORY 6/2017Rev. 0 to Rev. A Changes to Frequency Update Sequence Section ...................... 30 10/2016Revision 0Initial Version Rev. A Page 2 of 35