Clock Generator PLL with Integrated VCO Data Sheet ADF4360-9 FEATURES GENERAL DESCRIPTION Primary output frequency range: 65 MHz to 400 MHz The ADF4360-9 is an integrated integer-N synthesizer and Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz voltage-controlled oscillator (VCO). External inductors set the 3.0 V to 3.6 V power supply ADF4360-9 center frequency. This allows a VCO frequency 1.8 V logic compatibility range of between 65 MHz and 400 MHz. Integer-N synthesizer An additional divider stage allows division of the VCO signal. Programmable output power level The CMOS level output is equivalent to the VCO signal divided 3-wire serial interface by the integer value between 2 and 31. This divided signal can Digital lock detect be further divided by 2, if desired. Software power-down mode Control of all the on-chip registers is through a simple 3-wire APPLICATIONS interface. The device operates with a power supply ranging System clock generation from 3.0 V to 3.6 V and can be powered down when not in use. Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AV DV R DD DD SET ADF4360-9 LD 14-BIT R REF IN COUNTER LOCK MUTE DETECT CLK 24-BIT 24-BIT DATA CHARGE FUNCTION DATA CP REGISTER PUMP LATCH LE PHASE V VCO COMPARATOR V TUNE L1 L2 C C C N RF A OUT VCO OUTPUT 13-BIT B CORE STAGE COUNTER RF B OUT N = B DIVIDE-BY-A (2 TO 31) DIVIDE-BY-2 DIVOUT MULTIPLEXER AGND DGND CPGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07139-001ADF4360-9 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 10 Applications ....................................................................................... 1 VCO ............................................................................................. 11 General Description ......................................................................... 1 Output Stage ................................................................................ 12 Functional Block Diagram .............................................................. 1 DIVOUT Stage............................................................................ 12 Revision History ............................................................................... 2 Latch Structure ........................................................................... 13 Specifications ..................................................................................... 3 Power-Up ..................................................................................... 17 Timing Characteristics ................................................................ 5 Control Latch .............................................................................. 18 Absolute Maximum Ratings ............................................................ 6 N Counter Latch ......................................................................... 19 Transistor Count ........................................................................... 6 R Counter Latch ......................................................................... 19 ESD Caution .................................................................................. 6 Applications Information .............................................................. 20 Pin Configuration and Function Descriptions ............................. 7 Choosing the Correct Inductance Value ................................. 20 Typical Performance Characteristics ............................................. 8 Encode Clock for ADC .............................................................. 20 Circuit Description ......................................................................... 10 GSM Test Clock .......................................................................... 21 Reference Input Section ............................................................. 10 Interfacing ................................................................................... 22 N Counter .................................................................................... 10 PCB Design Guidelines for Chip Scale Package .................... 22 R Counter .................................................................................... 10 Output Matching ........................................................................ 23 PFD and Charge Pump .............................................................. 10 Outline Dimensions ....................................................................... 24 Lock Detect ................................................................................. 10 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/2016Rev. C to Rev. D Changed ADF4360 Family to ADF4360-9 and ADSP-21xx to ADSP-2181 ........................................... Throughout Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 11/2012Rev. B to Rev. C Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 24 2/2012Rev. A to Rev. B Added EPAD Note ............................................................................ 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 3/2008Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Figure 23 ...................................................................... 14 Changes to Output Matching Section .......................................... 23 1/2008Revision 0: Initial Version Rev. D Page 2 of 24