Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF4371 FEATURES GENERAL DESCRIPTION RF output frequency range: 62.5 MHz to 32,000 MHz The ADF4371 allows implementation of fractional-N or Integer N Fractional-N synthesizer and Integer N synthesizer phase-locked loop (PLL) frequency synthesizers when used with High resolution 39-bit fractional modulus an external loop filter and an external reference frequency. The Typical spurious PFD: 90 dBc wideband microwave voltage controlled oscillator (VCO) design Integrated rms jitter: 38 fs (1 kHz to 100 MHz) allows frequencies from 62.5 MHz to 32 GHz to be generated. Normalized phase noise floor: 234 dBc/Hz The ADF4371 has an integrated VCO with a fundamental output PFD operation to 250 MHz frequency ranging from 4000 MHz to 8000 MHz. In addition, the Reference frequency operation to 600 MHz VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output circuits that allows the user to generate radio frequency (RF) output 62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at 8,000 MHz to 16,000 MHz output at RF16x RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler 16,000 MHz to 32,000 MHz output at RF32x generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x Lock time approximately 3 ms with automatic calibration duplicates the frequency range of RF8x or permits direct access to Lock time <30 s with autocalibration bypassed the VCO output. To suppress the unwanted products of frequency Analog and digital power supplies: 3.3 V multiplication, a harmonic filter exists between the multipliers and VCO power supply: 3.3 V and 5 V the output stages of RF16x and RF32x. RF output mute function Control of all on-chip registers is through a 3-wire interface. 7mm 7mm, 48-terminal LGA package The ADF4371 operates with analog and digital power supplies APPLICATIONS ranging from 3.15 V to 3.45 V, and 5 V for the VCO power Wireless infrastructure (multicarrier global system for supply. The ADF4371 also contains hardware and software mobile communication (MC-GSM), 5 G) power-down modes. Test equipment and instrumentation Clock generation Aerospace and defense FUNCTIONAL BLOCK DIAGRAM VCC CAL VCC VCO VCC LDO VCC X1 VCC X2 VCC X4 VCC MUX VCC 3V VDD NDIV VDD LS VCC LDO 3V VCC REF VDD PFD VDD VP MUX MUXOUT 5-BIT R 2 REFP 2 COUNTER DIVIDER DOUBLER RS SW REFN LOCK DETECT VCC REG OUT ADF4371 SCLK CHARGE DATA REGISTER CPOUT SDIO FUNCTION PUMP LATCH CS VTUNE PHASE TRACKING 16GHz FILTER TO 32GHz COMPARATOR RF32P OUTPUT 4 STAGE RF32N LOW TRACKING 8GHz NOISE FILTER TO 16GHz LDO INTEGER FRACTION MODULUS VCO RF16P OUTPUT REGISTER REGISTER REGISTER 2 CORE STAGE RF16N 62.5MHz TO 8000MHz THIRD-ORDER FRACTIONAL RF8P 1, 2, 4, 8, OUTPUT INTERPOLATOR 16, 32, 64 STAGE RF8N N COUNTER MUX 62.5MHz TO 8000MHz OUTPUT RFAUX8P MUX STAGE RFAUX8N GND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20192021 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 16982-001ADF4371 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PFD and Charge Pump .............................................................. 21 Applications ....................................................................................... 1 MUXOUT and Lock Detect ...................................................... 21 General Description ......................................................................... 1 Double Buffers ............................................................................ 21 Functional Block Diagram .............................................................. 1 VCO ............................................................................................. 21 Revision History ............................................................................... 2 VCO ALC Threshold ................................................................. 22 Specificat ions ..................................................................................... 4 Output Stage ................................................................................ 22 Timing Specifications .................................................................. 8 Doubler ........................................................................................ 23 Absolute Maximum Ratings ............................................................ 9 Quadrupler .................................................................................. 23 Thermal Resistance ...................................................................... 9 Phase Adjust and Spur Optimization by Using PHASE WORD ....................................................................................................... 23 Electrostatic Discharge (ESD) Ratings ...................................... 9 SPI ................................................................................................. 23 ESD Caution .................................................................................. 9 Device Setup .................................................................................... 25 Pin Configuration and Function Descriptions ........................... 10 Step 1: Set Up the SPI Interface ................................................ 25 Typical Performance Characteristics ........................................... 12 Step 2: Initialization Sequence .................................................. 25 Theory of Operation ...................................................................... 17 Step 3: Frequency Update Sequence ........................................ 25 RF Synthesizer, a Worked Example .......................................... 17 Applications Information .............................................................. 26 Reference Input Sensitivity ........................................................ 17 Power Supplies ............................................................................ 26 Reference Doubler and Reference Divider ............................. 18 PCB Design Guidelines for an LGA Package ......................... 26 Spurious Optimization and Fast Lock ..................................... 18 Output Matching ........................................................................ 26 Optimizing Jitter ......................................................................... 18 Register Summary .......................................................................... 27 Spur Mechanisms ....................................................................... 18 Register Details ............................................................................... 29 Lock Time .................................................................................... 18 Outline Dimensions ....................................................................... 50 Circuit Description ......................................................................... 20 Ordering Guide .......................................................................... 50 Reference Input ........................................................................... 20 RF N Divider ............................................................................... 20 REVISION HISTORY 9/2021Rev. 0 to Rev. A Changes to Table 18 ....................................................................... 31 Changes to Figure 1 .......................................................................... 1 Changes to Table 27, Table 28, and Table 29 ............................... 33 Changes to Table 1 ............................................................................ 4 Changes to Table 30 ....................................................................... 34 Changes to Table 3 and Table 4 ....................................................... 9 Changes to Table 31 and Table 32 ................................................ 35 Added Electrostatic Discharge (ESD) Ratings Section and Changes to Address: 0x23, Default: 0x00, Name: REG0023 Table 5 Renumbered Sequentially ................................................. 9 Section and Table 34 ...................................................................... 36 Changes to Table 6 .......................................................................... 10 Changes to Address: 0x25, Default: 0x07, Name: REG0025 Changes to Figure 16 Caption ...................................................... 13 Section and Table 36 ...................................................................... 37 Changes to RF Synthesizer, a Worked Example Section, Changes to Address: 0x28, Default: 0x03, Name: REG0028 Equation 1, and Equation 7 ........................................................... 17 Section, Table 39, Address: 0x2A, Default: 0x00, Name: Changes to Figure 35 and INT, FRAC, MOD, and R Counter REG002A Section, and Table 40 ................................................... 39 Relationship Section ....................................................................... 20 Changes to Table 41 ....................................................................... 40 Changes to R Counter Section ...................................................... 21 Changes to Table 43 ....................................................................... 41 Deleted Output Stage Mute Section ............................................. 22 Changed Address: 0x2E, Default: 0x12, Name: REG002E Section to Added VCO ALC Threshold Section........................................... 22 Address: 0x2E, Default: 0x10, Name: REG002E Section .......... 41 Changes to Output Stage Section ................................................. 22 Changes to Address: 0x2E, Default: 0x10, Name: REG002E Added Phase Adjust and Spur Optimization by Using Section and Table 44 ...................................................................... 41 PHASE WORD Section ................................................................ 23 Changed Address: 0x2F, Default: 0x94, Name: REG002F Section Changes to Step 3: Frequency Update Sequence Section .......... 25 to Address: 0x2F, Default: 0x92, Name: REG002F Section ....... 42 Changes to Table 10 ........................................................................ 27 Rev. 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