Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF5355 FEATURES GENERAL DESCRIPTION RF output frequency range: 54 MHz to 13,600 MHz The ADF5355 allows implementation of fractional-N or Fractional-N synthesizer and integer-N synthesizer integer-N phase-locked loop (PLL) frequency synthesizers High resolution 38-bit modulus when used with an external loop filter and an external reference Phase frequency detector (PFD) operation to 125 MHz frequency. The wideband microwave VCO design permits Reference frequency operation to 600 MHz frequency operation from 6.8 GHz to 13.6 GHz at one radio Maintains frequency lock over 40C to +85C frequency (RF) output. A series of frequency dividers at another Low phase noise, voltage controlled oscillator (VCO) frequency output permits operation from 54 MHz to 6800 MHz. Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output The ADF5355 has an integrated VCO with a fundamental Analog and digital power supplies: 3.3 V output frequency ranging from 3400 MHz to 6800 MHz. In Charge pump and VCO power supplies: 5.0 V, typical addition, the VCO frequency is connected to divide by 1, 2, 4, 8, Logic compatibility: 1.8 V 16, 32, or 64 circuits that allow the user to generate RF output Programmable dual modulus prescaler of 4/5 or 8/9 frequencies as low as 54 MHz. For applications that require Programmable output power level isolation, the RF output stage can be muted. The mute function RF output mute function is both pin and software controllable. Analog and digital lock detect Control of all on-chip registers is through a simple 3-wire interface. Supported in the ADIsimPLL design tool The ADF5355 operates with analog and digital power supplies APPLICATIONS ranging from 3.15 V to 3.45 V, with charge pump and VCO Wireless infrastructure (W-CDMA, TD-SCDMA, supplies from 4.75 V to 5.25 V. The ADF5355 also contains WiMAX, GSM, PCS, DCS, DECT) hardware and software power-down modes. Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM AV DV V R V CE AV DD DD P SET VCO V DD RF MULTIPLEXER MUXOUT 10-BIT R 2 REF A IN 2 COUNTER DIVIDER C 1 REG DOUBLER LOCK REF B IN DETECT C 2 REG CLK CHARGE CP OUT PUMP DATA DATA REGISTER FUNCTION LE LATCH PHASE COMPARATOR V TUNE V REF VCO V BIAS INTEGER FRACTION MODULUS 2 CORE REG REG REG V REGVCO OUTPUT RF B THIRD-ORDER OUT STAGE FRACTIONAL INTERPOLATOR PDB RF 1/2/4/8/ OUTPUT RF A+ OUT N COUNTER 16/32/64 STAGE RF A OUT ADF5355 MULTIPLEXER A CP SD A A GND GND GNDRF GND GNDVCO Figure 1. 4 Rev. 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Technical Support www.analog.com 12714-001ADF5355 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 4 ..................................................................................... 26 Applications ....................................................................................... 1 Register 5 ..................................................................................... 27 General Description ......................................................................... 1 Register 6 ..................................................................................... 28 Functional Block Diagram .............................................................. 1 Register 7 ..................................................................................... 30 Revision History ............................................................................... 3 Register 8 ..................................................................................... 31 Specifications ..................................................................................... 4 Register 9 ..................................................................................... 31 Timing Characteristics ................................................................ 7 Register 10 ................................................................................... 32 Absolute Maximum Ratings ............................................................ 8 Register 11 ................................................................................... 32 Transistor Count ........................................................................... 8 Register 12 ................................................................................... 33 ESD Caution .................................................................................. 8 Register Initialization Sequence ............................................... 33 Pin Configuration and Function Descriptions ............................. 9 Frequency Update Sequence ..................................................... 33 Typical Performance Characteristics ........................................... 11 RF SynthesizerA Worked Example ...................................... 34 Circuit Description ......................................................................... 16 Reference Doubler and Reference Divider ............................. 34 Reference Input ........................................................................... 16 Spurious Optimization and Fast Lock ..................................... 34 RF N Divider ............................................................................... 16 Optimizing Jitter ......................................................................... 35 Phase Frequency Detector (PFD) and Charge Pump ............ 17 Spur Mechanisms ....................................................................... 35 MUXOUT and Lock Detect ...................................................... 17 Lock Time.................................................................................... 35 Input Shift Registers ................................................................... 17 Applications Information .............................................................. 36 Program Modes .......................................................................... 18 Power Supplies ............................................................................ 36 VCO.............................................................................................. 18 Printed Circuit Board (PCB) Design Guidelines for a Chip- Scale Package .............................................................................. 36 Output Stage ................................................................................ 18 Output Matching ........................................................................ 37 Register Maps .................................................................................. 20 Outline Dimensions ....................................................................... 38 Register 0 ..................................................................................... 22 Ordering Guide .......................................................................... 38 Register 1 ..................................................................................... 23 Register 2 ..................................................................................... 24 Register 3 ..................................................................................... 25 Rev. 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