Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF5356 FEATURES GENERAL DESCRIPTION RF output frequency range: 53.125 MHz to 13,600 MHz The ADF5356 allows implementation of fractional-N or integer N Noise floor integer channel: 227 dBc/Hz phase-locked loop (PLL) frequency synthesizers when used with Noise floor fractional channel: 225 dBc/Hz an external loop filter and an external reference frequency. The Integrated rms jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output wideband microwave VCO design permits frequency operation Fractional-N synthesizer and integer N synthesizer from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A Pin compatible to the ADF5355 series of frequency dividers at another frequency output permits High resolution, 52-bit modulus operation from 53.125 MHz to 6800 MHz. Phase frequency detector (PFD) operation to 125 MHz The ADF5356 has an integrated VCO with a fundamental Reference input frequency operation to 600 MHz output frequency ranging from 3400 MHz to 6800 MHz. In Maintains frequency lock over 40C to +85C addition, the VCO frequency is connected to divide by 1, 2, 4, 8, Low phase noise, voltage controlled oscillator (VCO) 16, 32, or 64 circuits that allow the user to generate RF output Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output frequencies as low as 53.125 MHz. For applications that require Analog and digital power supplies: 3.3 V isolation, the RF output stage can be muted. The mute function Charge pump and VCO power supplies: 5.0 V typical is both pin- and software-controllable. Logic compatibility: 1.8 V Control of all on-chip registers is through a simple 3-wire interface. Programmable output power level The ADF5356 operates with analog and digital power supplies RF output mute function ranging from 3.15 V to 3.45 V, with charge pump and VCO Supported by the ADIsimPLL design tool supplies from 4.75 V to 5.25 V. The ADF5356 also contains APPLICATIONS hardware and software power-down modes. Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS) Point to point and point to multipoint microwave links Satellites and very small aperture terminals (VSATs) Test equipment and instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM AV DV V R V CE AV DD DD P SET VCO V DD RF MULTIPLEXER MUXOUT 10-BIT R 2 REF A IN 2 DIVIDER COUNTER C 1 REG DOUBLER LOCK REF B IN DETECT C 2 REG CHARGE CLK CP OUT PUMP DATA DATA REGISTER FUNCTION PHASE LE LATCH COMPARATOR V TUNE V REF V VCO BIAS 2 CORE INTEGER FRACTION MODULUS REG REG REG V REGVCO OUTPUT RFOUTB STAGE THIRD-ORDER FRACTIONAL INTERPOLATOR PDB RF 1/2/4/8/ A+ RF OUTPUT OUT 16/32/64 STAGE A N COUNTER RF OUT ADF5356 MULTIPLEXER A CP SD A A GND GND GNDRF GND GNDVCO Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 15360-001ADF5356 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 3 ..................................................................................... 23 Applications ....................................................................................... 1 Register 4 ..................................................................................... 24 General Description ......................................................................... 1 Register 5 ..................................................................................... 25 Functional Block Diagram .............................................................. 1 Register 6 ..................................................................................... 26 Revision History ............................................................................... 2 Register 7 ..................................................................................... 28 Specif icat ions ..................................................................................... 3 Register 8 ..................................................................................... 29 Timing Characteristics ................................................................ 6 Register 9 ..................................................................................... 29 Absolute Maximum Ratings ............................................................ 7 Register 10 ................................................................................... 30 Thermal Resistance ...................................................................... 7 Register 11 ................................................................................... 31 Transistor Count ........................................................................... 7 Register 12 ................................................................................... 31 ESD Caution .................................................................................. 7 Register 13 ................................................................................... 32 Pin Configuration and Function Descriptions ............................. 8 Register Initialization Sequence ............................................... 32 Typical Performance Characteristics ........................................... 10 Frequency Update Sequence ..................................................... 33 Theory of Operation ...................................................................... 15 RF SynthesizerA Worked Example ...................................... 33 Reference Input Section ............................................................. 15 Reference Doubler and Reference Divider ............................. 34 RF N Divider ............................................................................... 15 Spurious Optimization and Fast Lock ..................................... 34 Phase Frequency Detector (PFD) and Charge Pump ............ 16 Optimizing Jitter ......................................................................... 34 MUXOUT and Lock Detect ...................................................... 16 Spur Mechanisms ....................................................................... 34 Input Shift Registers ................................................................... 16 PLL Lock Time ........................................................................... 34 Program Modes .......................................................................... 17 Applications Information .............................................................. 36 VCO.............................................................................................. 17 Power Supplies ............................................................................ 36 Output Stage ................................................................................ 17 PCB Design Guidelines for a Chip Scale Package ................. 36 Register Maps .................................................................................. 19 Output Matching ........................................................................ 37 Register 0 ..................................................................................... 21 Outline Dimensions ....................................................................... 38 Register 1 ..................................................................................... 22 Ordering Guide .......................................................................... 38 Register 2 ..................................................................................... 22 REVISION HISTORY 8/2017Revision 0: Initial Version Rev. 0 Page 2 of 38