Low Capacitance, 16- and 8-Channel, 15 V/+12 V iCMOS Multiplexers Data Sheet ADG1206/ADG1207 FEATURES FUNCTIONAL BLOCK DIAGRAMS <1 pC charge injection over full signal range ADG1206 ADG1207 1.5 pF off capacitance S1 S1A 33 V supply range DA 120 on resistance S8A Fully specified at 15 V/+12 V D 3 V logic-compatible inputs S1B Rail-to-rail operation DB Break-before-make switching action S16 S8B 28-lead TSSOP and 32-lead, 5 mm 5 mm LFCSP 1-OF-16 1-OF-8 APPLICATIONS DECODER DECODER Audio and video routing A0 A1 A2 A3 EN A0 A1 A2 EN Automatic test equipment Figure 1. Data acquisition systems Battery-powered systems Sample-and-hold systems Communication systems GENERAL DESCRIPTION The ultralow capacitance and exceptionally low charge injection The ADG1206 and ADG1207 are monolithic iCMOS analog multiplexers comprising sixteen single channels and eight of these multiplexers make them ideal solutions for data acquisition differential channels, respectively. The ADG1206 switches one and sample-and-hold applications, where low glitch and fast of sixteen inputs to a common output, as determined by the settling are required. Figure 2 shows that there is minimum 4-bit binary address lines A0, A1, A2, and A3. The ADG1207 charge injection over the entire signal range of the device. switches one of eight differential inputs to a common differential iCMOS construction also ensures ultralow power dissipation, output, as determined by the 3-bit binary address lines A0, A1, making the devices ideally suited for portable and battery- powered instruments. and A2. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. When 1.0 MUX (SOURCE TO DRAIN) on, each channel conducts equally well in both directions and T = 25C A 0.9 has an input signal range that extends to the supplies. 0.8 The industrial CMOS (iCMOS) modular manufacturing 0.7 process combines high voltage, complementary metal-oxide 0.6 semiconductor (CMOS) and bipolar technologies. It enables the V = +15V DD 0.5 V = 15V SS development of a wide range of high performance analog ICs 0.4 capable of 33 V operation in a footprint that no other generation 0.3 V = +12V of high voltage devices has been able to achieve. Unlike analog DD V = 0V SS ICs using conventional CMOS processes, iCMOS components 0.2 can tolerate high supply voltages while providing increased 0.1 V = +5V DD V = 5V performance, dramatically lower power consumption, and SS 0 reduced package size. 15 10 5 0 5 10 15 V (V) S Figure 2. Source-to-Drain Charge Injection vs. Source Voltage Rev. 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CHARGE INJECTION (pC) 06119-002 06119-001ADG1206/ADG1207 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ............................8 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 12 Revision History ............................................................................... 2 Terminology .................................................................................... 16 Specif icat ions ..................................................................................... 3 Test Circuits ..................................................................................... 17 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 19 Single Supply ................................................................................. 5 Ordering Guide .......................................................................... 19 REVISION HISTORY 6/2016Rev. B to Rev. C Changes to Analog Inputs Parameter, Table 3 .............................. 7 Added Digital Inputs Parameter, Table 3 ...................................... 7 4/2016Rev. A to Rev. B Changed CP-32-2 to CP-32-7 ...................................... Throughout Changes to Figure 3, Figure 4, and Table 4 ................................... 8 Changes to Figure 5, Figure 6, and Table 6 ................................. 10 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 3/2009Rev. 0 to Rev. A Change to IDD Parameter, Table 1 ................................................... 4 Change to IDD Parameter, Table 2 ................................................... 6 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 7/2006Revision 0: Initial Version Rev. C Page 2 of 20