Low Capacitance, 4-/8-Channel, 15 V/+12 V iCMOS Multiplexers Data Sheet ADG1208/ADG1209 FEATURES FUNCTIONAL BLOCK DIAGRAMS <1 pC charge injection over full signal range ADG1208 ADG1209 1 pF off capacitance S1 S1A 33 V supply range DA S4A 120 on resistance Fully specified at 15 V/+12 V D 3 V logic compatible inputs S1B Rail-to-rail operation DB Break-before-make switching action S8 S4B Available in a 16-lead TSSOP, a 16-lead LFCSP, and a 1-OF-8 1-OF-4 16-lead SOIC DECODER DECODER Typical power consumption < 0.03 W A0 A1 A2 EN A0 A1 EN APPLICATIONS Figure 1. Audio and video routing Automatic test equipment Data-acquisition systems Battery-powered systems Sample-and-hold systems Communication systems GENERAL DESCRIPTION The ADG1208 and ADG1209 are monolithic, iCMOS analog The ultralow capacitance and exceptionally low charge injection multiplexers comprising eight single channels and four differential of these multiplexers make them ideal solutions for data acquisition channels, respectively. The ADG1208 switches one of eight inputs and sample-and-hold applications, where low glitch and fast to a common output as determined by the 3-bit binary address settling are required. Figure 2 shows that there is minimum lines A0, A1, and A2. The ADG1209 switches one of four charge injection over the entire signal range of the device. differential inputs to a common differential output as determined iCMOS construction also ensures ultralow power dissipation, by the 2-bit binary address lines A0 and A1. An EN input on making the devices ideally suited for portable and battery- powered instruments. both devices enable or disable the device. When disabled, all channels are switched off. When on, each channel conducts 1.0 MUX (SOURCE TO DRAIN) equally well in both directions and has an input signal range T = 25C A 0.9 that extends to the supplies. 0.8 The industrial CMOS (iCMOS) modular manufacturing 0.7 process combines high voltage complementary metal-oxide 0.6 semiconductor (CMOS) and bipolar technologies. It enables the V = +15V DD 0.5 V = 15V SS development of a wide range of high performance analog ICs 0.4 capable of 33 V operation in a footprint that no other generation 0.3 of high voltage devices has been able to achieve. Unlike analog V = +12V DD V = 0V SS ICs using conventional CMOS processes, iCMOS components 0.2 can tolerate high supply voltages while providing increased 0.1 V = +5V DD V = 5V performance, dramatically lower power consumption, and SS 0 reduced package size. 15 10 5 0 5 10 15 V (V) S Figure 2. Source to Drain Charge Injection vs. Source Voltage Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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CHARGE INJECTION (pC) 05713-001 05713-051ADG1208/ADG1209 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................8 Functional Block Diagrams ............................................................. 1 Typical Performance Characteristics ........................................... 12 General Description ......................................................................... 1 Terminology .................................................................................... 16 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 17 Specifications ..................................................................................... 3 Outline Dimensions ....................................................................... 20 Dual Supply ................................................................................... 3 Ordering Guide .......................................................................... 21 Single Supply ................................................................................. 5 Absolute Maximum Ratings ............................................................ 7 REVISION HISTORY 6/2016Rev. D to Rev. E 1/2009Rev. A to Rev. B Changes to Analog Inputs Parameter, Table 3 .............................. 7 Change to IDD Parameter, Table 1 .................................................... 4 Added Digital Inputs Parameter, Table 3 ...................................... 7 Change to IDD Parameter, Table 2 .................................................... 6 Moved Figure 7 ............................................................................... 10 Change to Table 7 ........................................................................... 10 4/2007Rev. 0 to Rev. A Deleted Table 8 Renumbered Sequentially ................................ 11 Added 16-lead SOIC .......................................................... Universal Updated Outline Dimensions ....................................................... 20 Changes to Table 1 ............................................................................. 3 Changes to Ordering Guide .......................................................... 21 Changes to Table 2 ............................................................................. 5 Changes to Figure 10 and Figure 11............................................. 10 3/2016Rev. C to Rev. D Updated Outline Dimensions ....................................................... 17 Changes to Table 4 Title ................................................................... 8 Changes to Ordering Guide .......................................................... 18 Changes to Table 5 Title ................................................................... 9 Changes to Table 7 Title ................................................................. 10 4/2006Revision 0: Initial Version Changes to Figure 7 ........................................................................ 11 Added Table 8 Renumbered Sequentially .................................. 11 Changes to Table 9 Title ................................................................. 12 8/2015Rev. B to Rev. C Changes to Features Section............................................................ 1 Added Figure 4 Renumbered Sequentially .................................. 8 Changes to Table 4 ............................................................................ 8 Changes to Figure 5 .......................................................................... 9 Added Table 5 Renumbered Sequentially .................................... 9 Added Figure 7 ................................................................................ 10 Changes to Table 7 .......................................................................... 10 Changes to Figure 8 ........................................................................ 11 Added Table 8 .................................................................................. 11 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 Rev. 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