Low Capacitance, Low Charge Injection, 15 V/+12 V iCMOS Dual SPST Switches Data Sheet ADG1221/ADG1222/ADG1223 FEATURES FUNCTIONAL BLOCK DIAGRAM <0.5 pC charge injection over full signal range ADG1221 ADG1222 Off capacitance: 2 pF S1 S1 Off leakage: 2 pA IN1 IN1 Supply range: 33 V D1 D1 D2 On resistance: 120 D2 IN2 Fully specified at 15 V, +12 V IN2 S2 S2 No V supply required L 3 V logic-compatible inputs Rail-to-rail operation 10-lead MSOP package ADG1223 APPLICATIONS S1 IN1 Automatic test equipment D1 Data acquisition systems D2 Battery-powered systems IN2 Sample-and-hold systems S2 Audio signal routing Video signal routing SWITCHES SHOWN FOR A LOGIC 0 INPUT Communication systems Figure 1. GENERAL DESCRIPTION ADG1222. The ADG1223 has one switch with digital control The ADG1221/ADG1222/ADG1223 are monolithic, complemen- logic similar to that of the ADG1221 the logic is inverted on tary metal-oxide semiconductor (CMOS) devices containing the other switch. The ADG1223 exhibits break-before-make four independently selectable switches designed on an iCMOS switching action for use in multiplexer applications. Each (industrial CMOS) process. iCMOS is a modular manufacturing switch conducts equally well in both directions when on and process combining high voltage CMOS and bipolar technologies. has an input signal range that extends to the supplies. In the off It enables the development of a wide range of high performance condition, signal levels up to the supplies are blocked. analog ICs, capable of 33 V operation, in a footprint that no 0.5 previous generation of high voltage parts has been able to achieve. T = 25C A Unlike analog ICs using conventional CMOS processes, iCMOS 0.4 V = +15V components can tolerate high supply voltages while providing DD 0.3 V = 15V SS increased performance, dramatically lower power consumption, 0.2 and reduced package size. 0.1 The ultralow capacitance and exceptionally low charge injection 0 of these switches make them ideal solutions for data acquisition V = 12V DD 0.1 V = 0V SS and sample-and-hold applications, where low glitch and fast 0.2 settling are required. Figure 2 shows that there is minimum 0.3 charge injection over the full signal range of the device. V = +5V DD 0.4 V = 5V SS The ADG1221/ADG1222/ADG1223 contain two independent 0.5 15 10 5 0 5 10 15 single-pole/single-throw (SPST) switches. The ADG1221 and INPUT VOLTAGE (V) ADG1222 differ only in that the digital control logic is inverted. Figure 2. Charge Injection vs. Input Voltage The ADG1221 switches are turned on with Logic 1 on the appro- priate control input, and Logic 0 is required for the Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. CHARGE INJECTION (pC) 06574-041 06574-001ADG1221/ADG1222/ADG1223 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions ..............................7 General Description ......................................................................... 1 Terminology .......................................................................................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specifications ..................................................................................... 3 Test Circuits ..................................................................................... 13 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 15 Single Supply ................................................................................. 4 Ordering Guide .......................................................................... 15 Absolute Maximum Ratings ............................................................ 6 REVISION HISTORY 9/2017Rev. A to Rev. B Change to Features Section ............................................................. 1 3/2009Rev. 0 to Rev. A Changes to Power Requirements, I , Digital Inputs = 5 V DD Parameter, Table 1 ............................................................................. 4 Changes to t Parameter and Power Requirements, I , Digital ON DD Inputs = 5 V Parameter, Table 2 ...................................................... 5 2/2007Rev. 0: Initial Version Rev. B Page 2 of 16