Serially Controlled, 15 V/+12 V/5 V, 8-Channel/ 4-Channel, iCMOS Multiplexers/Matrix Switches Data Sheet ADG1438/ADG1439 FEATURES FUNCTIONAL BLOCK DIAGRAMS Serial interface up to 50 MHz ADG1438 SDO daisy-chaining option S1 9.5 on resistance at 25C 1.6 on-resistance flatness Fully specified at 15 V/+12 V/5 V D 3 V logic-compatible inputs Rail-to-rail operation 20-lead TSSOP and 20-lead, 4 mm 4 mm LFCSP S8 APPLICATIONS INPUT SHIFT SDO Relay replacement REGISTER Audio and video routing Automatic test equipment RESET SCLK SYNC DIN Data acquisition systems Figure 1. Temperature measurement systems Avionics ADG1439 Battery-powered systems S1A Communication systems DA Medical equipment S4A GENERAL DESCRIPTION The ADG1438 and ADG1439 are CMOS analog matrix switches S1B DB with a serially controlled 3-wire interface. The ADG1438 is an S4B 8-channel matrix switch, and the ADG1439 is a dual 4-channel matrix switch. INPUT SHIFT SDO REGISTER The ADG1438/ADG1439 use a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible SCLK SYNC DIN RESET with standard SPI, QSPI, MICROWIRE, and DSP interface Figure 2. standards. The output of the shift register, SDO, enables a number of the ADG1438/ADG1439 devices to be daisy-chained. On PRODUCT HIGHLIGHTS power-up, the internal shift register contains all zeros, and all 1. 50 MHz serial interface. switches are in the off state. 2. 9.5 on resistance. Each switch conducts equally well in both directions when on, 3. 1.6 on-resistance flatness. making these devices suitable for both multiplexing and 4. 3 V logic-compatible digital input, VINH = 2.0 V, VINL = 0.8 V. demultiplexing applications. Because each switch is turned on or off by a separate bit, these devices can also be configured as a Table 1. Related Devices type of switch array, where any, all, or none of the eight switches Device No. Description can be closed at any time. The input signal range extends to the ADG1408/ADG1409 Low on resistance, parallel interface, 4-/8-channel 15 V supply rails. All channels exhibit break-before-make switching multiplexers action, preventing momentary shorting when switching channels. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08496-001 08496-002ADG1438/ADG1439 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 10 Applications ....................................................................................... 1 ESD Caution................................................................................ 10 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 11 Functional Block Diagrams ............................................................. 1 Typical Performance Characteristics ........................................... 13 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 16 Revision History ............................................................................... 2 Terminology .................................................................................... 18 Specifications ..................................................................................... 3 Theory of Operation ...................................................................... 19 15 V Dual Supply ....................................................................... 3 Serial Interface ............................................................................ 19 12 V Single Supply ........................................................................ 5 Input Shift Register .................................................................... 19 5 V Dual Supply ......................................................................... 7 Power-On Reset .......................................................................... 19 Continuous Current per Channel .............................................. 8 Daisy-Chaining ........................................................................... 19 Timing Characteristics ................................................................ 9 Outline Dimensions ....................................................................... 20 Timing Diagrams .......................................................................... 9 Ordering Guide .......................................................................... 20 Absolute Maximum Ratings .......................................................... 10 REVISION HISTORY 3/16Rev. A to Rev. B Changed CP-20-4 to CP-20-10 .................................... Throughout Changes to Figure 5, Figure 6, and Table 10 ............................... 11 Changes to Figure 7, Figure 8, and Table 11 ............................... 12 Changes to Figure 29 ...................................................................... 16 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 5/10Rev. 0 to Rev. A Changes to Channel On Leakage, ID, IS (On) +25C Parameter, Table 2 .................................................................................... 3 10/09Revision 0: Initial Version Rev. B Page 2 of 20