High Voltage, Latch-Up Proof, 8-/16-Channel Multiplexers Data Sheet ADG5206/ADG5207 FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up proof ADG5206 3.5 pF off source capacitance S1 Off drain capacitance ADG5206: 64 pF D ADG5207: 33 pF 0.35 pC typical charge injection 0.02 nA on channel leakage S16 Low on resistance: 155 typical 9 V to 22 V dual-supply operation 1-OF-16 DECODER 9 V to 40 V single-supply operation V to V analog signal range SS DD A0 A1 A2 A3 EN Human body model (HBM) ESD rating Figure 1. ADG5206: 8 kV all pins ADG5207: 8 kV I/O port to supplies ADG5207 S1A APPLICATIONS DA S8A Automatic test equipment Data acquisition Instrumentation S1B Avionics DB S8B Battery monitoring Communication systems 1-OF-8 DECODER A0 A1 A2 EN Figure 2. GENERAL DESCRIPTION The ADG5206 and ADG5207 are monolithic CMOS analog The ADG5206/ADG5207 do not have V pins instead, an on-chip L multiplexers comprising 16 single channels and 8 differential voltage generator generates the logic power supply internally. channels, respectively. The ADG5206 switches one of sixteen PRODUCT HIGHLIGHTS inputs to a common output, as determined by the 4-bit binary address lines, A0, A1, A2, and A3. The ADG5207 switches one 1. Trench Isolation Guards Against Latch-Up. A dielectric trench of eight differential inputs to a common differential output, as separates the P and N channel transistors to prevent latch-up determined by the 3-bit binary address lines, A0, A1, and A2. even under severe overvoltage conditions. 2. Optimal switch design for low charge injection, low switch An EN input on both devices enables or disables the device. When capacitance, and low leakage currents. EN is low, the device is disabled and all channels switch off. The 3. The ADG5206 achieves 8 kV HBM ESD specification on ultralow capacitance and charge injection of these switches make all external pins, while the ADG5207 achieves 8 kV on the them ideal solutions for data acquisition and sample-and-hold I/O port to supply pins, 2 kV on the I/O port to I/O port applications, where low glitch and fast settling are required. Fast pins, and 8 kV on all other pins. switching speed coupled with high signal bandwidth make these 4. Dual-Supply Operation. For applications where the analog devices suitable for video signal switching. signal is bipolar, the ADG5206/ADG5207 can be operated Each switch conducts equally well in both directions when on, from dual supplies of up to 22 V. and each switch has an input signal range that extends to the 5. Single-Supply Operation. For applications where the power supplies. In the off condition, signal levels up to the analog signal is unipolar, the ADG5206/ADG5207 can be supplies are blocked. operated from a single rail power supply of up to 40 V. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 10714-001 10714-002ADG5206/ADG5207 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 11 Applications ....................................................................................... 1 ESD Caution................................................................................ 11 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 12 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 16 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 21 Revision History ............................................................................... 2 Terminology .................................................................................... 23 Specifications ..................................................................................... 3 Applications Information .............................................................. 24 15 V Dual Supply ....................................................................... 3 Trench Isolation .......................................................................... 24 20 V Dual Supply ....................................................................... 4 Outline Dimensions ....................................................................... 25 12 V Single Supply ........................................................................ 6 Ordering Guide .......................................................................... 25 36 V Single Supply ........................................................................ 8 Continuous Current per Channel, Sx, D, or Dx ..................... 10 REVISION HISTORY 5/13Rev. 0 to Rev. A Added 32-Lead LFCSP ....................................................... Universal Changes to Features Section and Product Highlights Section .......... 1 Moved Continuous Current per Channel, Sx, D, or Dx Section, Table 5, and Table 6 ......................................................................... 10 Changes to Table 7 ........................................................................... 11 Changes to Figure 3 ......................................................................... 12 Changes to Figure 5 ......................................................................... 13 Changes to Figure 30, Figure 32, and Figure 33 .......................... 22 7/12Revision 0: Initial Version Rev. A Page 2 of 28