ADG528FBPZ Analog Devices

8-Channel Fault-Protected Analog Multiplexer ADG528F FEATURES FUNCTIONAL BLOCK DIAGRAM Low on resistance (300 typical) ADG528F Fast switching times t : 250 ns maximum ON S1 t : 250 ns maximum OFF Low power dissipation (3.3 mW maximum) Fault and overvoltage protection (40 V to +55 V) D All switches off with power supply off Analog output of on channel clamped within power supplies if an overvoltage occurs S8 Latch-up proof construction WR 1 OF 8 Break-before-make construction DECODER RS TTL and CMOS compatible inputs A0 A1 A2 EN APPLICATIONS Figure 1. Existing multiplexer applications (both fault-protected and nonfault-protected) New designs requiring multiplexer functions GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1 The ADG528F is a CMOS analog multiplexer, with the 1. Fault protection. comprising eight single channels. This multiplexer provides The ADG528F can withstand continuous voltage inputs fault protection. Using a series n-channel, p-channel, n-channel from 40 V to +55 V. When a fault occurs due to the MOSFET structure, both device and signal source protection is power supplies being turned off, all the channels are turned provided in the event of an overvoltage or power loss. The off and only a leakage current of a few nanoamperes flows. multiplexer can withstand continuous overvoltage inputs 2. On channel turns off while fault exists. from 40 V to +55 V. During fault conditions, the multiplexer 3. Low R . ON input (or output) appears as an open circuit and only a few 4. Fast switching times. nanoamperes of leakage current will flow. This protects not 5. Break-before-make switching. only the multiplexer and the circuitry driven by the multiplexer, Switches are guaranteed break-before-make so that input but also protects the sensors or signal sources that drive the signals are protected against momentary shorting. multiplexer. 6. Trench isolation eliminates latch-up. A dielectric trench separates the p-channel and n-channel The ADG528F switches one of eight inputs to a common output MOSFETs thereby preventing latch-up. as determined by the 3-bit binary address lines A0, A1, and A2. The ADG528F has on-chip address and control latches that facilitate microprocessor interfacing. An EN input on the device is used to enable or disable the device. When disabled, all channels are switched off. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20012011 Analog Devices, Inc. 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Trademarks and registered trademarks are the property of their respective owners. 09655-001ADG528F TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions ..............................7 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8 Product Highlights ........................................................................... 1 Terminology .................................................................................... 10 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 11 Specif icat ions ..................................................................................... 3 Test Circuits ..................................................................................... 12 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 15 Truth Table .................................................................................... 4 Ordering Guide .......................................................................... 15 Timing Diagrams .......................................................................... 5 REVISION HISTORY 7/11Rev. E to Rev. F Deleted ADG508F/ADG509F .......................................... Universal Changes to Table 3 ............................................................................ 6 Added Table 4 .................................................................................... 7 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 7/09Rev. D to Rev. E Updated Format .................................................................. Universal Added TSSOP ..................................................................... Universal Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 18 4/01Data Sheet Changed from Rev. C to Rev. D. Changes to Ordering Guide ............................................................ 1 Changes to Specifications Table ...................................................... 2 Max Ratings Changed ...................................................................... 4 Deleted 16-Lead Cerdip from Outline Dimensions .................. 11 Deleted 18-Lead Cerdip from Outline Dimensions .................. 12 Rev. F Page 2 of 16