Fault Protection and Detection, 10 R , Dual SPDT Switch ON Data Sheet ADG5436F FEATURES FUNCTIONAL BLOCK DIAGRAM Overvoltage protection up to 55 V and +55 V ADG5436F Power-off protection up to 55 V and +55 V S1A S2A Overvoltage detection on source pins D1 D2 Interrupt flags indicate fault status S1B S2B Low on resistance: 10 (typical) On-resistance flatness of 0.5 (maximum) 6 kV human body model (HBM) ESD rating FAULT SF DETECTION Latch-up immune under any circumstance + FF SWITCH DRIVER Known state without digital inputs present V to V analog signal range SS DD IN1 IN2 EN DR 5 V to 22 V dual supply operation NOTES 1. SWITCHES SHOWN FOR A LOGIC 1 INPUT. 8 V to 44 V single-supply operation Fully specified at 15 V, 20 V, +12 V, and +36 V Figure 1. APPLICATIONS Analog input/output modules Process control/distributed control systems Data acquisition Instrumentation Avionics Automatic test equipment Communication systems Relay replacement GENERAL DESCRIPTION The ADG5436F is an analog multiplexer, containing two resistance of the ADG5436F, combined with the on-resistance independently selectable single-pole, double-throw (SPDT) flatness over a significant portion of the signal range, makes it switches. An EN input is used to disable all the switches. For use an ideal solution for data acquisition and gain switching in multiplexer applications, both switches exhibit break-before- applications where excellent linearity and low distortion are make switching action. critical. Note that, throughout this data sheet, the dual function pin names Each channel conducts equally well in both directions when on, and each switch has an input signal range that extends to the are referenced only by the relevant function where applicable. See supplies. The digital inputs are compatible with 3 V logic inputs the Pin Configurations and Function Descriptions section for over the full operating supply range. full pin names and function descriptions. When no power supplies are present, the switch remains in the off PRODUCT HIGHLIGHTS condition, and the channel inputs are high impedance. Under 1. Source pins are protected against voltages greater than the normal operating conditions, if the analog input signal level on supply rails, up to 55 V and +55 V. any Sxx pin exceeds V or V by a threshold voltage, V , the DD SS T 2. Source pins are protected against voltages between 55 V channel turns off and that Sxx pin becomes high impedance. If and +55 V in an unpowered state. the channel is on, the drain pin reacts according to the drain 3. Overvoltage detection with digital output indicates the response (DR) input pin. If the DR pin is left floating or pulled operating state of the switches. high, the drain remains high impedance and floats. If the DR pin 4. Trench isolation guards against latch-up. is pulled low, the drain pulls to the exceeded rail. Input signal 5. Optimized for low on resistance and on-resistance flatness. levels of up to +55 V or 55 V relative to ground are blocked, in 6. The ADG5436F operates from a dual supply of 5 V up to both the powered and unpowered conditions. The low on 22 V, or a single power supply of 8 V up to 44 V. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152017 Analog Devices, Inc. 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Technical Support www.analog.com 12882-001ADG5436F Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 20 Applications ....................................................................................... 1 Terminology .................................................................................... 24 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 26 General Description ......................................................................... 1 Switch Architecture .................................................................... 26 Product Highlights ........................................................................... 1 Fault Protection .......................................................................... 27 Revision History ............................................................................... 2 Applications Information .............................................................. 28 Specifications ..................................................................................... 3 Power Supply Rails ..................................................................... 28 15 V Dual Supply ....................................................................... 3 Power Supply Sequencing Protection ...................................... 28 20 V Dual Supply ....................................................................... 5 Signal Range ................................................................................ 28 12 V Single Supply ........................................................................ 7 Low Impedance Channel Protection ....................................... 28 36 V Single Supply ........................................................................ 9 Power Supply Recommendations ............................................. 28 Continuous Current per Channel, Sxx or Dx ......................... 11 High Voltage Surge Suppression .............................................. 28 Absolute Maximum Ratings .......................................................... 12 Intelligent Fault Detection ........................................................ 29 ESD Caution ................................................................................ 12 Large Voltage, High Frequency Signals ................................... 29 Pin Configurations and Function Descriptions ......................... 13 Outline Dimensions ....................................................................... 30 Truth Tables for Switches .......................................................... 14 Ordering Guide .......................................................................... 30 Typical Performance Characteristics ........................................... 15 REVISION HISTORY 10/2017Rev. B to Rev. C 5/2015Rev. 0 to Rev. A Changes to Fault Drain Leakage Current With Overvoltage Added 16-Lead LFCSP Package ....................................... Universal Parameter, Table 1 ............................................................................. 3 Changes to Table 1 ............................................................................. 3 Changes to Fault Drain Leakage Current With Overvoltage Changes to Table 2 ............................................................................. 5 Parameter, Table 2 ............................................................................. 7 Changes to Table 3 ............................................................................. 7 Changes to Fault Drain Leakage Current With Overvoltage Changes to Table 4 ............................................................................. 9 Parameter, Table 4 ............................................................................ 9 Changes to Table 5 .......................................................................... 11 Updated Outline Dimensions ....................................................... 30 Changes to Table 6 .......................................................................... 12 Added Figure 3 Renumbered Sequentially ................................ 13 Changes to Ordering Guide .......................................................... 30 Changes to Table 7 .......................................................................... 13 1/2016Rev. A to Rev. B Added Figure 53 ............................................................................. 30 Changes to Table 1 ............................................................................ 3 Updated Outline Dimensions ....................................................... 30 Changes to Table 2 ............................................................................ 5 Changes to Ordering Guide .......................................................... 30 Changes to Table 3 ............................................................................ 7 Changes to Table 4 ............................................................................ 9 1/2015Revision 0: Initial Version Changes to ESD Performance Section ......................................... 26 Rev. C Page 2 of 30