3 V/5 V, 4/8 Channel High a Performance Analog Multiplexers ADG608/ADG609 FUNCTIONAL BLOCK DIAGRAMS FEATURES +3 V, +5 V, 65 V Power Supplies ADG608 ADG609 V to V Analog Signal Range SS DD Low On Resistance (30 V max) S1 S1A Fast Switching Times DA S4A t 75 ns max ON t 45 ns max OFF D Low Power Dissipation (1.5 mW max) Break-Before-Make Construction S1B ESD > 5000 V as per Military Standard 3015.7 DB S8 S4B TTL and CMOS Compatible Inputs 1 OF 4 1 OF 8 APPLICATIONS DECODER DECODER Automatic Test Equipment Data Acquisition Systems A0 A1 A2 EN A0 A1 EN Communication Systems Avionics and Military Systems Microprocessor Controlled Analog Systems The ability to operate from single +3 V, +5 V or 5 V bipolar Medical Instrumentation supplies makes the ADG608 and ADG609 perfect for use in Battery Powered Instruments battery operated instruments and with the new generation of Remote Powered Equipment DACs and ADCs from Analog Devices. The use of 5 V sup- Compatible with 65 V DACs and ADCs such as plies and reduced operating currents gives much lower power AD7840/8, AD7870/1/2/4/5/6/8 dissipation than devices operating from 15 V supplies. GENERAL DESCRIPTION The ADG608 and ADG609 are monolithic CMOS analog mul- PRODUCT HIGHLIGHTS tiplexers comprising eight single channels and four differential 1. Extended Signal Range channels respectively, fully specified for 5 V, +5 V and +3 V The ADG608/ADG609 are fabricated on an enhanced 2 power supplies. The ADG608 switches one of eight inputs to a LC MOS process giving an increased signal range which common output as determined by the 3-bit binary address lines extends to the supplies. A0, A1 and A2. The ADG609 switches one of four differential 2. Low Power Dissipation inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both de- 3. Low R ON vices is used to enable or disable the device. When disabled, all 4. Fast Switching Times channels are switched OFF. All the address and enable inputs 5. Break-Before-Make Switching are TTL compatible over the full specified operating tempera- Switches are guaranteed break-before-make so that input ture range, making the parts suitable for bus-controlled systems signals are protected against momentary shorting. such as data acquisition systems, process controls, avionics and ATEs since the TTL compatible address inputs simplify the digital 6. Single/Dual Supply Operation interface design and reduce the board space requirements. 2 ORDERING GUIDE The ADG608/ADG609 are designed on an enhanced LC MOS process that provides low power dissipation yet gives high Model Temperature Range Package Option* switching speed and low on resistance. Each channel conducts ADG608BN 40C to +85C N-16 equally well in both directions when ON and has an input signal ADG608BR 40C to +85C R-16A range which extends to the supplies. In the OFF condition, sig- ADG608BRU 40C to +85C RU-16 nal levels up to the supplies are blocked. All channels exhibit ADG608TRU 55C to +125C RU-16 break-before-make switching action preventing momentary shorting when switching channels. Inherent in the design is low ADG609BN 40C to +85C N-16 charge injection for minimum transients when switching the ADG609BR 40C to +85C R-16A digital inputs. ADG609BRU 40C to +85C RU-16 *N = Plastic DIP RU = Thin Shrink Small Outline Package (TSSOP) R = 0.15 Small Outline IC (SOIC). REV. A Information furnished by Analog Devices is believed to be accurate and Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703ADG608/ADG609SPECIFICATIONS 1 (V = +5 V 6 10%, V = 5 V 6 10%, GND = 0 V, unless otherwise noted) DUAL SUPPLY DD SS Parameter B Version T Version +258C 40C to +258C 558C to Test Conditions/ +858C +1258C Units Comments ANALOG SWITCH Analog Signal Range V to V V to V V SS DD SS DD R 22 22 typ 3.5 V < V < +3.5 V, I = 1 mA ON S S 30 35 30 40 max V = +4.5 V, V = 4.5 V DD SS Test Circuit 1 R 56 5 6 max 3 V < V < +3 V, I = 1 mA ON S DS V = +5 V, V = 5 V DD SS R Match 2 3 2 3 max V = 0 V, I = 1 mA ON S DS V = +5 V, V = 5 V DD SS LEAKAGE CURRENTS V = +5.5 V, V = 5.5 V DD SS Source OFF Leakage I (OFF) 0.05 0.05 nA typ V = 4.5 V, V = 74.5 V S D S 0.5 2 0.5 10 nA max Test Circuit 2 Drain OFF Leakage I (OFF) 0.05 0.05 nA typ V = 4.5 V, V = 74.5 V D D S ADG608 0.5 2 0.5 10 nA max Test Circuit 3 ADG609 0.5 1 0.5 5 nA max Channel ON Leakage I , I (ON) 0.05 0.05 nA typ V = V = 4.5 V D S S D ADG608 0.5 3 0.5 20 nA max Test Circuit 4 ADG609 0.5 1.5 0.5 10 nA max DIGITAL INPUTS Input High Voltage, V 2.4 2.4 V min INH Input Low Voltage, V 0.8 0.8 V max INL Input Current I or I 1 1 A max V = 0 or V INL INH IN DD C , Digital Input Capacitance 5 5 pF typ IN 2 DYNAMIC CHARACTERISTICS t 50 50 ns typ R = 300 , C = 35 pF TRANSITION L L 75 90 75 100 ns max V = 3.5 V, V = 73.5 V S1 S8 Test Circuit 5 t 10 10 ns min R = 300 , C = 35 pF OPEN L L V = +3.5 V Test Circuit 6 S t (EN) 50 50 ns typ R = 300 , C = 35 pF ON L L 75 90 75 100 ns max V = +3.5 V Test Circuit 7 S t (EN) 30 30 ns typ R = 300 , C = 35 pF OFF L L 45 60 45 75 ns max V = +3.5 V Test Circuit 7 S Charge Injection 6 6 pC typ V = 0 V, R = 0 , C = 1 nF S S L Test Circuit 8 OFF Isolation 85 85 dB typ R = 1 k, C = 15 pF, f = 100 kHz L L V = 3 V rms Test Circuit 9 S Channel-to-Channel Crosstalk 85 85 dB typ R = 1 k, C = 15 pF, f = 100 kHz L L Test Circuit 10 C (OFF) 9 9 pF typ S C (OFF) D ADG608 40 40 pF typ ADG609 20 20 pF typ C (ON) D ADG608 54 54 pF typ ADG609 34 34 pF typ POWER REQUIREMENTS I 0.05 0.2 0.05 0.2 A typ V = 0 V or V DD IN DD 0.2 2 0.2 2 A max I 0.01 0.1 0.01 0.1 A typ SS 0.1 1 0.1 1 A max NOTES 1 Temperature ranges are as follows: B Version: 40C to +85C T Version: 55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. 2 REV. A