SPI Interface, 4 SPST Switches, 9.8 R , 20 V/+36 V, Mux Configurable ON Data Sheet ADGS5412 FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface with error detection ADGS5412 Includes CRC, invalid read/write address, and SCLK count error detection S1 D1 Supports burst mode and daisy-chain mode Industry standard SPI Mode 0 and Mode 3 interface S2 D2 compatible S3 D3 Guaranteed break-before-make switching allowing external wiring of switches to deliver multiplexer configurations S4 D4 V to V analog signal range SS DD Fully specified at 15 V, 20 V, +12 V, and +36 V 9 V to 22 V dual-supply operation SPI SDO INTERFACE 9 V to 40 V single-supply operation Latch-up proof analog switch pins 8 kV HBM ESD rating SCLK SDI CS RESET/V L Low on resistance (<10 ) Figure 1. 1.8 V logic compatibility with 2.7 V V 3.3 V L APPLICATIONS Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems GENERAL DESCRIPTION The ADGS5412 contains four independent single-pole/single- applications with external wiring. throw (SPST) switches. A serial peripheral interface (SPI) controls PRODUCT HIGHLIGHTS the switches. The SPI interface has robust error detection features, 1. SPI interface removes the need for parallel conversion and including cyclic redundancy check (CRC) error detection, invalid logic traces and reduces general-purpose input/output read/write address detection, and serial clock (SCLK) count (GPIO) channel count. error detection. 2. Daisy-chain mode removes additional logic traces when It is possible to daisy-chain multiple ADGS5412 devices together, multiple devices are used. which enables the configuration of multiple devices with a 3. CRC, invalid read/write address, and SCLK count error minimal amount of digital lines. The ADGS5412 can also detection ensure a robust digital interface. operate in burst mode to decrease the time between SPI 4. CRC error detection capabilities allow for the use of the commands. ADGS5412 in safety critical systems. Each switch conducts equally well in both directions when on, 5. Guaranteed break-before-make switching allows the use of and each switch has an input signal range that extends to the the ADGS5412 in multiplexer configurations with external supplies. In the off condition, signal levels up to the supplies are wiring. blocked. Trench isolation analog switch section guards against latch-up. A The on-resistance profile is very flat over the full analog input dielectric trench separates the positive (P) and negative (N) channel range, which ensures good linearity and low distortion when transistors thereby preventing latch-up even under severe switching audio signals. The ADGS5412 exhibits break-before- overvoltage conditions. make switching action, allowing use of the device in multiplexer Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20172018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 15234-001ADGS5412 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Error Detection Features ........................................................... 22 Applications ....................................................................................... 1 Clearing the Error Flags Register ............................................. 23 Functional Block Diagram .............................................................. 1 Burst Mode .................................................................................. 23 General Description ......................................................................... 1 Software Reset ............................................................................. 23 Product Highlights ........................................................................... 1 Daisy-Chain Mode ..................................................................... 23 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 24 Specifications ..................................................................................... 3 Break-Before-Make Switching .................................................. 25 15 V Dual Supply ....................................................................... 3 Trench Isolation .......................................................................... 25 20 V Dual Supply ....................................................................... 5 Digital Input Buffers .................................................................. 25 12 V Single Supply ........................................................................ 7 Applications Information .............................................................. 26 36 V Single Supply ........................................................................ 9 Power Supply Rails ..................................................................... 26 Continuous Current per Channel, S or D ............................ 11 Power Supply Recommendations ............................................. 26 X X Timing Characteristics .............................................................. 11 Register Summary .......................................................................... 27 Absolute Maximum Ratings .......................................................... 13 Register Details ............................................................................... 28 ESD Caution ................................................................................ 13 Switch Data Register .................................................................. 28 Pin Configurations and Function Descriptions ......................... 14 Error Configuration Register .................................................... 28 Typical Performance Characteristics ........................................... 15 Error Flags Register .................................................................... 29 Test Circuits ..................................................................................... 19 Burst Enable Register ................................................................. 29 Terminology .................................................................................... 21 Software Reset Register ............................................................. 29 Theory of Operation ...................................................................... 22 Outline Dimensions ....................................................................... 30 Address Mode ............................................................................. 22 Ordering Guide .......................................................................... 30 REVISION HISTORY 7/2018Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Source Off Leakage, I (Off) Parameter and Drain S Off Leakage, I (Off) Parameter, Table 1 ....................................... 3 D Changes to Source Off Leakage, IS (Off) Parameter and Drain Off Leakage, ID (Off) Parameter, Table 2 ....................................... 5 Changes to Source Off Leakage, IS (Off) Parameter and Drain Off Leakage, ID (Off) Parameter, Table 4 ....................................... 9 Deleted Figure 43 and Figure 44 Renumbered Sequentially ..... 24 Added Figure 43 and Figure 44 Renumbered Sequentially ..... 24 5/2017Revision 0: Initial Version Rev. A Page 2 of 30