DC to 2.0 GHz Multiplier Data Sheet ADL5391 FEATURES FUNCTIONAL BLOCK DIAGRAM YMNS YPLS GADJ Ultrafast symmetric multiplier Function: V = (V V )/1 V + V W X Y Z XPLS ZMNS Unique design ensures absolute XY-symmetry XMNS ZPLS Identical X and Y amplitude/timing responses WPLS Adjustable gain scaling, DC-coupled throughout, 3 dB bandwidth of 2 GHz ENBL WMNS Fully differential inputs, may be used single ended ADL5391 VMID Low noise, high linearity W = XY/1V+Z Accurate, temperature stable gain scaling COMM VPOS Single-supply operation (4.5 V to 5.5 V at 130 mA) Low current power-down mode Figure 1. 16-lead LFCSP APPLICATIONS Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control GENERAL DESCRIPTION are ac-coupled, their nominal voltage will be VPOS/2. These input The ADL5391 draws on three decades of experience in interfaces each present a differential 500 input impedance up to advanced analog multiplier products. It provides the same approximately 700 MHz, decreasing to 50 at 2 GHz. The gain general mathematical function that has been field proven to scaling input, GADJ, can be used for fine adjustment of the gain provide an exceptional degree of versatility in function synthesis. scaling constant () about unity. V = (V V )/ 1 V + V W X Y Z The differential output can swing 2 V about the V /2 POS The most significant advance in the ADL5391 is the use of a common-mode and can be taken in a single-ended fashion as new multiplier core architecture, which differs markedly from well. The output common mode is designed to interface directly the conventional form that has been in use since 1970. The to the inputs of another ADL5391. Light dc loads can be ground conventional structure that employs a current mode, translinear referenced however, ac-coupling of the outputs is recommended core is fundamentally asymmetric with respect to the X and Y for heavy loads. inputs, leading to relative amplitude and timing misalignments that are problematic at high frequencies. The new multiplier core The ENBL pin allows the ADL5391 to be disabled quickly to a eliminates these misalignments by offering symmetric signal standby mode. It operates off supply voltages from 4.5 V to 5.5 V paths for both X and Y inputs. The Z input allows a signal to be while consuming approximately 130 mA. added directly to the output. This can be used to cancel a carrier The ADL5391 is fabricated on Analog Devices, Inc. proprietary, or to apply a static offset voltage. high performance, 65 GHz, SOI complementary, SiGe bipolar The fully differential X, Y, and Z input interfaces are operational IC process. It is available in a 16-lead, RoHS compliant, LFCSP over a 2 V range, and they can be used in single-ended fashion. and operates over a 40C to +85C temperature range. The user can apply a common mode at these inputs to vary Evaluation boards are available. from the internally set V /2 down to ground. If these inputs POS Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06059-001ADL5391 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 10 Functional Block Diagram .............................................................. 1 Basic Theory ............................................................................... 10 General Description ......................................................................... 1 Basic Connections ...................................................................... 10 Revision History ............................................................................... 2 Evaluation Board ............................................................................ 13 Specif icat ions ..................................................................................... 3 Outline Dimensions ....................................................................... 15 Absolute Maximum Ratings ............................................................ 5 Ordering Guide .......................................................................... 15 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 10/2017Rev. 0 to Rev. A Changed CP-16-3 to CP-16-27 .................................... Throughout Added EPAD, Table 3 ....................................................................... 6 Changed General Description to Theory of Operation ............ 10 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 7/2006Revision 0: Initial Version Rev. A Page 2 of 15