HEF4521BT,653 Nexperia

HEF4521B 24-stage frequency divider and oscillator Rev. 8 3 December 2021 Product data sheet 1. General description The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous master reset input (MR), and an input circuit that allows three modes of operation. The single inverting stage (A2 to Y2) functions as: a crystal oscillator, an input buffer for an external oscillator or in combination with A1 as an RC oscillator. The crystal oscillator operates in Low-power mode when pins V and V are supplied via external resistors. SS1 DD1 Each flip-flop divides the frequency of the previous flip-flop by two, consequently the HEF4521B 24 counts up to 2 = 16777216. The counting advances on the HIGH-to-LOW transition of the 18 24 clock (A2). The outputs from each of the last seven stages (2 to 2 ) are available for additional flexibility. It operates over a recommended V power supply range of 3 V to 15 V referenced to V (usually DD SS ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Low power crystal oscillator operation Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4521BT -40 C to +85 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mmNexperia HEF4521B 24-stage frequency divider and oscillator 4. Functional diagram 5 4 2 9 V Y2 MR A1 DD1 A2 6 CP STAGES 1 to 8 C V D Q8 SS1 3 CP STAGES 9 to 16 C D Q16 CP STAGES 17 to 24 C D Q24 Q18 Q19 Q20 Q21 Q22 Q23 Y1 1 10 11 12 13 14 15 7 001aae708 Fig. 1. Functional diagram V DD1 V DD A2 to FFs to logic V SS V SS1 Y2 001aae711 Fig. 2. Schematic diagram of clock input circuitry HEF4521B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 3 December 2021 2 / 15