3 V LVDS Quad CMOS Differential Line Receiver ADN4668 FEATURES FUNCTIONAL BLOCK DIAGRAM V CC 15 kV ESD protection on receiver input pins 400 Mbps (200 MHz) switching rates ADN4668 R IN1+ Flow-through pin configuration simplifies PCB layout R1 R OUT1 R IN1 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) R IN2+ 2.7 ns maximum propagation delay R2 R OUT2 R IN2 3.3 V power supply High impedance outputs on power-down R IN3+ R3 R OUT3 Low power design (3 mW quiescent typical) R IN3 Interoperable with existing 5 V LVDS drivers Accepts small swing (310 mV typical) differential R IN4+ R4 R OUT4 input signal levels R IN4 Supports open, short, and terminated input fail-safe EN EN 0 V to 100 mV threshold region Conforms to TIA/EIA-644 LVDS standard GND Industrial operating temperature range of 40C to +85C Figure 1. Available in 16-lead surface-mount SOIC and 16-lead low profile TSSOP package APPLICATIONS Point-to-point data transmission Multidrop buses Clock distribution networks Backplane receivers GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential The ADN4668 also offers active-high and active-low enable/disable signaling (LVDS) line receiver offering data rates of over 400 Mbps inputs (EN and EN) that control all four receivers. They disable (200 MHz) and ultralow power consumption. It features a flow- the receivers and switch the outputs to a high impedance state. through pin configuration for easy PCB layout and separation This high impedance state allows the outputs of one or more of input and output signals. ADN4668s to be multiplexed together and reduces the quies- The device accepts low voltage (310 mV typical) differential cent power consumption to 3 mW typical. input signals and converts them to a single-ended, 3 V TTL/CMOS The ADN4668 and its companion driver, the ADN4667, offer logic level. a new solution to high speed, point-to-point data transmission and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL). Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07237-001ADN4668 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Enable Inputs .............................................................................. 11 Specif icat ions ..................................................................................... 3 Applications Information .......................................................... 11 AC Characteristics ........................................................................ 4 Outline Dimensions ....................................................................... 12 Test Circuits and Waveforms ...................................................... 4 Ordering Guide .......................................................................... 12 Absolute Maximum Ratings ............................................................ 6 REVISION HISTORY 7/08Rev. 0 to Rev. A Added 16-Lead SOIC N .................................................... Universal Changes to Table 1 ............................................................................ 3 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 3/08Revision 0: Initial Version Rev. A Page 2 of 12