3.3 V, 200 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E FEATURES FUNCTIONAL BLOCK DIAGRAMS V CC Multipoint LVDS transceivers (low voltage differential signaling driver and receiver pairs) ADN4691E/ ADN4696E Switching rate: 200 Mbps (100 MHz) RO R Supported bus loads: 30 to 55 RE A Choice of 2 receiver types B DE Type 1 (ADN4691E/ADN4693E): hysteresis of 25 mV Type 2 (ADN4696E/ADN4697E): threshold offset of 100 mV DI D for open-circuit and bus-idle fail-safe GND Conforms to TIA/EIA-899 standard for M-LVDS Figure 1. Glitch free power-up/power-down on M-LVDS bus V CC Controlled transition times on driver output Common-mode range: 1 V to +3.4 V, allowing ADN4693E/ ADN4697E communication with 2 V of ground noise A RO R Driver outputs high-Z when disabled or powered off B Enhanced ESD protection on bus pins RE 15 kV HBM (human body model), air discharge DE Z 8 kV HBM (human body model), contact discharge D DI Y 10 kV IEC 61000-4-2, air discharge 8 kV IEC 61000-4-2, contact discharge GND Operating temperature range: 40C to +85C Figure 2. Available in 8-lead (ADN4691E/ADN4696E) and 14-lead (ADN4693E/ADN4697E) SOIC packages APPLICATIONS Backplane and cable multipoint data transmission Multipoint clock distribution Low power, high speed alternative to shorter RS-485 links Networking and wireless base station infrastructure GENERAL DESCRIPTION The ADN4691E/ADN4693E/ADN4696E/ADN4697E are The devices are available as half-duplex in an 8-lead SOIC package multipoint, low voltage differential signaling (M-LVDS) (the ADN4691E/ADN4696E) or as full-duplex in a 14-lead transceivers (driver and receiver pairs) that can operate at up to SOIC package (the ADN4693E/ADN4697E). A selection table 200 Mbps (100 MHz). The receivers detect the bus state with a for the ADN4690E to ADN4697E devices is shown in Table 1. differential input of as little as 50 mV over a common-mode Table 1. ADN4690E to ADN4697E Selection Table voltage range of 1 V to +3.4 V. ESD protection of up to 15 kV Part No. Receiver Data Rate SOIC Duplex is implemented on the bus pins. The devices adhere to the ADN4690E Type 1 100 Mbps 8-lead Half TIA/EIA-899 standard for M-LVDS and complement TIA/EIA- ADN4691E Type 1 200 Mbps 8-lead Half 644 LVDS devices with additional multipoint capabilities. ADN4692E Type 1 100 Mbps 14-lead Full The ADN4691E/ADN4693E are Type 1 receivers with 25 mV of ADN4693E Type 1 200 Mbps 14-lead Full hysteresis so that slow-changing signals or loss of input does not ADN4694E Type 2 100 Mbps 8-lead Half lead to output oscillations. The ADN4696E/ADN4697E are ADN4695E Type 2 100 Mbps 14-lead Full Type 2 receivers exhibiting an offset threshold, guaranteeing the ADN4696E Type 2 200 Mbps 8-lead Half output state when the bus is idle (bus-idle fail-safe) or the inputs are ADN4697E Type 2 200 Mbps 14-lead Full open (open-circuit fail-safe). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com 10355-002 10355-001ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Voltage and Current Measurements ............................ 11 Applications ....................................................................................... 1 Driver Timing Measurements .................................................. 12 Functional Block Diagrams ............................................................. 1 Receiver Timing Measurements ............................................... 13 General Description ......................................................................... 1 Theory of Operation ...................................................................... 14 Revision History ........................................................................... 2 Half-Duplex/Full-Duplex Operation ....................................... 14 Specifications ..................................................................................... 3 Three-State Bus Connection ..................................................... 14 Receiver Input Threshold Test Voltages .................................... 4 Truth Tables................................................................................. 14 Timing Specifications .................................................................. 5 Glitch-Free Power-Up/Power-Down ....................................... 15 Absolute Maximum Ratings ............................................................ 6 Fault Conditions ......................................................................... 15 Thermal Resistance ...................................................................... 6 Receiver Input Thresholds/Fail-Safe ........................................ 15 ESD Caution .................................................................................. 6 Applications Information .............................................................. 16 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 17 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 17 Test Circuits and Switching Characteristics ................................ 11 REVISION HISTORY 1/16Rev. A to Rev. B Added Table 7 ....................................................................................6 Change to Table 6 ............................................................................. 6 Changes to Table 8 ............................................................................. 7 Changes to Figure 33 ...................................................................... 13 3/12Rev. 0 to Rev. A Added Table 12 ............................................................................... 14 Added ADN4691E and ADN4693E ................................. Universal Changes to Receiver Input Thresholds/Fail-Safe Section Changes to Features Section, General Description Section, and Figure 36 ................................................................................... 15 and Table 1 ......................................................................................... 1 Changes to Ordering Guide .......................................................... 17 Added Type 1 Receiver Parameters, Table 2 ................................. 3 Added Table 3, Renumbered Sequentially .................................... 4 12/11Revision 0: Initial Version Added Type 1 Receiver Parameters, Table 5 ................................. 5 Rev. B Page 2 of 20