Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs Data Sheet ADP5040 FEATURES GENERAL DESCRIPTION Input voltage range: 2.3 V to 5.5 V The ADP5040 combines one high performance buck regulator One 1.2 A buck regulator and two low dropout regulators (LDO) in a small 20-lead Two 300 mA LDOs LFCSP to meet demanding performance and board space 20-lead, 4 mm 4 mm LFCSP package requirements. Overcurrent and thermal protection The high switching frequency of the buck regulator enables the use Soft start of tiny multilayer external components and minimizes board space. Undervoltage lockout When the MODE pin is set to logic high, the buck regulator Buck key specifications operates in forced pulse width modulation (PWM) mode. When Output voltage range: 0.8 V to 3.8 V the MODE pin is set to logic low, the buck regulator operates in Current mode topology for excellent transient response PWM mode when the load is around the nominal value. When 3 MHz operating frequency the load current falls below a predefined threshold the regulator Peak efficiency up to 96% operates in power save mode (PSM) improving the light-load Uses tiny multilayer inductors and capacitors efficiency. The low quiescent current, low dropout voltage, and Mode pin selects forced PWM or auto PWM/PSM modes wide input voltage range of the ADP5040 LDOs extend the 100% duty cycle low dropout mode battery life of portable devices. The ADP5040 LDOs maintain LDOs key specifications a power supply rejection greater than 60 dB for frequencies as Output voltage range: 0.8 V to 5.2 V high as 10 kHz while operating with a low headroom voltage. Low V from 1.7 V to 5.5 V IN Stable with 2.2 F ceramic output capacitors Each regulator in the ADP5040 is activated by a high level on High PSRR the respective enable pin. The output voltages of the regulators Low output noise are programmed though external resistor dividers to address a Low dropout voltage variety of applications. 40C to +125C junction temperature range FUNCTIONAL BLOCK DIAGRAM VOUT1 L1 AVIN 1H SW V AT OUT1 1.2A FB1 BUCK AVIN C6 R1 R2 10F VIN1 V = 2.3V TO IN1 5.5V PGND C5 EN BK 4.7F ON FPWM MODE EN1 OFF PSM/PWM VOUT2 V AT LDO1 OUT2 VIN2 V = 1.7V IN2 (DIGITAL) 300mA FB2 TO 5.5V C1 C2 EN LDO1 R3 1F 2.2F R4 ON EN2 OFF ON EN3 OFF EN LDO2 VOUT3 VIN3 V AT V = 1.7V IN3 OUT3 LDO2 300mA TO 5.5V FB3 C3 (ANALOG) C4 1F R7 2.2F R3 AGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09665-001ADP5040 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Management Unit ........................................................... 25 General Description ......................................................................... 1 Buck Section ................................................................................ 26 Functional Block Diagram .............................................................. 1 LDO Section ............................................................................... 27 Revision History ............................................................................... 2 Applications Information .............................................................. 29 Specif icat ions ..................................................................................... 3 Buck External Component Selection ....................................... 29 General Specifications ................................................................. 3 LDO External Component Selection ...................................... 30 Buck Specifications ....................................................................... 3 Power Dissipation/Thermal Considerations ............................. 31 LDO1, LDO2 Specifications ....................................................... 4 Application Diagram ................................................................. 33 Input and Output Capacitor, Recommended Specifications .. 5 PCB Layout Guidelines .................................................................. 34 Absolute Maximum Ratings ............................................................ 6 Suggested Layout ........................................................................ 34 Thermal Resistance ...................................................................... 6 Bill of Materials ........................................................................... 35 ESD Caution .................................................................................. 6 Factory Programmable Options ................................................... 36 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 37 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 37 Theory of Operation ...................................................................... 25 REVISION HISTORY 1/2014Rev. 0 to Rev. A 5/2019Rev. C to Rev. D Change to Figure 1 ............................................................................ 1 Changes to Figure 106 .................................................................... 30 Change to Figure 106 ..................................................................... 30 Change to Figure 108 ..................................................................... 33 4/2018Rev. B to Rev. C Change to Figure 109 ..................................................................... 34 Updated Outline Dimensions ....................................................... 37 Changes to Ordering Guide .......................................................... 37 12/2011Revision 0: Initial Version 3/2017Rev. A to Rev. B Changes to Figure 2 and Table 7 ..................................................... 8 Rev. D Page 2 of 37