2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs Data Sheet ADP5076 The ADP5076 includes a fixed internal or resistor programmable FEATURES soft start timer to prevent inrush current at power-up. Input supply voltage range: 2.85 V to 5.5 V Generates well regulated, independently resistor Other key safety features in the ADP5076 include overcurrent programmable V and V outputs protection (OCP), overvoltage protection (OVP), thermal POS NEG Boost regulator to generate V output shutdown (TSD), and input undervoltage lockout (UVLO). POS Adjustable positive output to 35 V The ADP5076 is available in a 20-ball wafer level chip scale Integrated 2.0 A main switch package (WLCSP) and is rated for a 40C to +125C junction Inverting regulator to generate V output NEG temperature range. Adjustable negative output to 30 V Table 1. Family Models Integrated 1.20 A main switch 1.2 MHz or 2.4 MHz switching frequency with optional Boost Inverter Model Switch (A) Switch (A) Package external frequency synchronization from 1.0 MHz to ADP5070 1.0 0.6 20-lead LFCSP (4 mm 2.6 MHz 4 mm) and 20-lead TSSOP Resistor programmable soft start timer ADP5071 2.0 1.2 20-lead LFCSP (4 mm Slew rate control for lower system noise 4 mm) and 20-lead TSSOP Individual precision enable and flexible start-up sequence 20-ball WLCSP ADP5072 1.0 0.6 control for symmetric start, V first, or V first POS NEG (1.61 mm 2.18 mm) Out of phase operation 1 ADP5073 N/A 1.2 16-lead LFCSP (3 mm UVLO, OCP, OVP, and TSD protection 3 mm) 1.61 mm 2.18 mm, 20-ball WLCSP 1 ADP5074 N/A 2.4 16-lead LFCSP (3 mm 40C to +125C junction temperature range 3 mm) 1 ADP5075 N/A 0.8 12-ball WLCSP APPLICATIONS (1.61 mm 2.18 mm) Bipolar amplifiers, ADCs, DACs, and multiplexers ADP5076 2.0 1.2 20-ball WLCSP Charge coupled device (CCD) bias supply (1.61 mm 2.18 mm) 1 Optical module supply N/A means not applicable. RF power amplifier bias FUNCTIONAL BLOCK DIAGRAM Time of flight module supply V IN GENERAL DESCRIPTION ADP5076 L1 SS The ADP5076 is a dual, high performance, dc-to-dc regulator that V POS R C1 SW1 generates independently regulated positive and negative rails. The COMP1 D1 C SW1 C1 input voltage range of 2.85 V to 5.5 V supports a wide variety of R FT1 EN1 FB1 applications. The integrated main switch in both regulators enables R FB1 C OUT1 generation of an adjustable positive output voltage up to +35 V and PVIN V PVIN IN a negative output voltage down to 30 V. PGND AVIN C IN PGND C VREF The ADP5076 operates at a pin selected 1.2 MHz or 2.4 MHz VREF EN2 switching frequency. The ADP5076 can synchronize with an R C OUT2 FB2 R external oscillator from 1.0 MHz to 2.6 MHz to ease noise C2 FB2 COMP2 R filtering in sensitive applications. Both regulators implement FT2 C C2 SYNC programmable slew rate control circuitry for the metal-oxide SW2 SLEW V NEG D2 semiconductor field effect transistor (MOSFET) driver stage to SEQ AGND L2 reduce electromagnetic interference (EMI). Flexible start-up sequencing is provided with the options of manual enable, Figure 1. simultaneous mode, positive supply first, and negative supply first. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 20402-001ADP5076 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Precision Enabling ..................................................................... 14 Applications ....................................................................................... 1 Soft Start ...................................................................................... 14 General Description ......................................................................... 1 Slew Rate Control ....................................................................... 14 Functional Block Diagram .............................................................. 1 Current-Limit Protection .......................................................... 14 Revision History ............................................................................... 2 Overvoltage Protection .............................................................. 14 Specif icat ions ..................................................................................... 3 Thermal Shutdown .................................................................... 14 Absolute Maximum Ratings ............................................................ 5 Startup Sequence ........................................................................ 14 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 16 ESD Caution .................................................................................. 5 Component Selection ................................................................ 16 Pin Configuration and Function Descriptions ............................. 6 Output Capacitors ...................................................................... 17 Typical Performance Characteristics ............................................. 7 Loop Compensation .................................................................. 18 Theory of Operation ...................................................................... 13 Common Applications .............................................................. 20 Pulse Width Modulation (PWM) Mode ................................. 13 Layout Considerations ............................................................... 22 Pulse Skip Modulation Mode ................................................... 13 Outline Dimensions ....................................................................... 23 UVLO ........................................................................................... 13 Ordering Guide .......................................................................... 23 Oscillator and Synchronization ................................................ 13 Internal Regulator ...................................................................... 13 REVISION HISTORY 12/2019Rev. 0 to Rev. A Replaced Figure 1 ............................................................................. 1 Replaced Figure 39 ......................................................................... 13 8/2019Revision 0: Initial Version Rev. A Page 2 of 23