Keypad Decoder and I/O Port Expander Data Sheet ADP5586 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND 16-element FIFO for event recording 10 configurable I/Os allowing for such functions as ADP5586 Keypad decoding for a matrix of up to 5 5 UVLO RST/R5 OSCILLATOR POR Key press/release interrupts SDA 2 GPIO functions I C INTERFACE SCL GPI with selectable interrupt level INT 100 k or 300 k pull-up resistors KEY SCAN 300 k pull-down resistors R0 AND GPO with push-pull or open drain DECODE R1 Programmable logic block GPI SCAN R2 REGISTERS AND Pulse generators R3 DECODE Periods and on times R4 I/O LOGIC CONFIG Above 30 sec in 125 ms increments C0 Up to 255 ms in 1 ms increments PULSE C1 GEN 1 Reset generator C2 PULSE 2 I C interface with Fast-mode Plus (Fm+) support of up to 1 MHz C3 GEN 2 C4 Open-drain interrupt output RESET GEN 16-ball WLCSP, 1.59 mm 1.59 mm Figure 1. APPLICATIONS Keypad entries and input/output expansion capabilities Smartphones, remote controls, and cameras Healthcare, industrial, and instrumentation GENERAL DESCRIPTION The ADP5586 is a 10-input/output port expander with a built-in as events via the FIFO, eliminating the need to monitor different keypad matrix decoder, programmable logic, reset generator, and registers for event changes. The ADP5586 is equipped with a pulse generators. Input/output expander ICs are used in portable FIFO to store up to 16 events. Events can be read back by the 2 devices (phones, remote controls, and cameras) and nonportable processor via an I C-compatible interface. applications (healthcare, industrial, and instrumentation). I/O The ADP5586 eliminates the need for the main processor to expanders can be used to increase the number of I/Os available monitor the keypad, thus reducing power consumption and/or to a processor or to reduce the number of I/Os required through increasing processor bandwidth for performing other functions. interface connectors for front panel designs. The programmable logic functions allow common logic require- The ADP5586 handles all key scanning and decoding and can ments to be integrated as part of the GPIO expander, thus saving flag the main processor, via an interrupt line, that new key events board area and cost. have occurred. GPI changes and logic changes can also be tracked Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 11148-001ADP5586 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Event FIFO .....................................................................................9 Applications ....................................................................................... 1 Key Scan Control ........................................................................ 10 Functional Block Diagram .............................................................. 1 GPI Input ..................................................................................... 13 General Description ......................................................................... 1 GPO Output ................................................................................ 13 Revision History ............................................................................... 2 Logic Block .................................................................................. 14 Specifications ..................................................................................... 3 Reset Block .................................................................................. 15 2 I C Timing Specifications ............................................................ 4 Interrupts ..................................................................................... 15 Absolute Maximum Ratings ............................................................ 5 Pulse Generators ......................................................................... 16 Thermal Resistance ...................................................................... 5 Register Interface ............................................................................ 17 ESD Caution .................................................................................. 5 Register Map ................................................................................... 19 Pin Configuration and Function Descriptions ............................. 6 Detailed Register Descriptions ................................................. 21 Theory of Operation ........................................................................ 7 Applications Schematic .................................................................. 41 Device Enable ................................................................................ 8 Outline Dimensions ....................................................................... 42 Device Overview .......................................................................... 8 Ordering Guide .......................................................................... 42 Functional Description .................................................................... 9 REVISION HISTORY 3/13Revision 0: Initial Version Rev. 0 Page 2 of 44