20 V, 500 mA, Low Noise, CMOS LDO Data Sheet ADP7104 FEATURES TYPICAL APPLICATION CIRCUITS Input voltage range: 3.3 V to 20 V V = 8V VIN VOUT V = 5V OUT IN + + CIN COUT Maximum output current: 500 mA 1F 1F SENSE Low noise: 15 V rms for fixed output versions RPG R1 PSRR performance of 60 dB at 10 kHz, V = 3.3 V ON OUT 100k 100k EN/ OFF Reverse current protection UVLO R2 PG PG Low dropout voltage: 350 mV at 500 mA 100k GND Initial accuracy: 0.8% Accuracy over line, load, and temperature 2% to +1%, T = 40C to +125C J Figure 1. ADP7104 with Fixed Output Voltage, 5 V 1.25% to +1%, T = 0C to +85C J V = 5V V = 8V VIN VOUT IN OUT Low quiescent current (V = 5 V), I = 900 A with 500 mA load IN GND + + CIN COUT 40.2k 1F 1F Low shutdown current: <40 A at V = 12 V, stable with small IN ADJ 13k 1 F ceramic output capacitor R1 ON 100k RPG EN/ 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, OFF 100k UVLO R2 PG PG 5 V, and 9 V 100k Adjustable output from 1.22 V to V V GND IN DO Foldback current limit and thermal overload protection User programmable precision UVLO/enable Figure 2. ADP7104 with Adjustable Output Voltage, 5 V Power-good indicator 8-lead LFCSP and 8-lead SOIC packages APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and PLLs Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7104 is a CMOS, low dropout linear regulator that oper- The ADP7104 output noise voltage is 15 V rms and is inde- ates from 3.3 V to 20 V and provides up to 500 mA of output pendent of the output voltage. A digital power-good output current. This high input voltage LDO is ideal for regulation of allows power system monitors to check the health of the output high performance analog and mixed signal circuits operating voltage. A user programmable precision undervoltage lockout from 19 V to 1.22 V rails. Using an advanced proprietary archi- function facilitates sequencing of multiple power supplies. tecture, it provides high power supply rejection, low noise, and The ADP7104 is available in 8-lead, 3 mm 3 mm LFCSP achieves excellent line and load transient response with just a and 8-lead SOIC packages. The LFCSP offers a very compact small 1 F ceramic output capacitor. solution and also provides excellent thermal performance for The ADP7104 is available in seven fixed output voltage options applications requiring up to 500 mA of output current in a and an adjustable version, which allows output voltages that range small, low-profile footprint. from 1.22 V to VIN VDO via an external feedback divider. Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09507-002 09507-001ADP7104 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Applications Information .............................................................. 17 Typical Application Circuits ............................................................ 1 Capacitor Selection .................................................................... 17 General Description ......................................................................... 1 Programmable Undervoltage Lockout (UVLO) .................... 18 Revision History ............................................................................... 2 Power-Good Feature .................................................................. 19 Specif icat ions ..................................................................................... 3 Noise Reduction of the Adjustable ADP7104 ............................ 19 Input and Output Capacitor, Recommended Specifications .. 4 Current Limit and Thermal Overload Protection ................. 20 Absolute Maximum Ratings ............................................................ 5 Thermal Considerations ............................................................ 20 Thermal Data ................................................................................ 5 Printed Circuit Board Layout Considerations ............................ 23 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 24 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 25 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 10/2019Rev. H to Rev. I 8/2013Rev. C to Rev. D Changes to Features Section............................................................ 1 Changes to Table 3 ............................................................................. 5 Changes to Table 1 ............................................................................ 3 Changes to Figure 59 and Figure 60 ............................................. 16 2/2013Rev. B to Rev. C Changes to Noise Reduction of the Adjustable ADP7104 Updated Outline Dimensions ....................................................... 24 S ection .............................................................................................. 19 10/2015Rev. G to Rev. H Updated Outline Dimensions ....................................................... 25 Changes to Figure 59 and Figure 60 ............................................. 16 3/2012Rev. A to Rev. B 5/2014Rev. F to Rev. G Changes to Figure 66 ...................................................................... 18 Change to UVLO Threshold Rising Parameter, Table 1 ............. 4 Change to Power-Good Feature Section ..................................... 19 11/2011Rev. 0 to Rev. A Changed Low Dropout Voltage from 200 mV to 350 mV ........... 1 11/2013Rev. E to Rev. F Changes to Dropout Voltage Parameter ......................................... 3 Changes to Figure 53 through Figure 58 ..................................... 15 10/2011Revision 0: Initial Version 10/2013Rev. D to Rev. E Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Figure 65 ...................................................................... 18 Changes to Figure 69 ...................................................................... 19 Rev. I Page 2 of 25