9 kHz to 30 GHz, Silicon SPDT Switch Data Sheet ADRF5021 FEATURES FUNCTIONAL BLOCK DIAGRAM RF2 Ultrawideband frequency range: 9 kHz to 30 GHz Nonreflective 50 design ADRF5021 VSS Low insertion loss: 2.0 dB to 30 GHz EN 50 High isolation: 60 dB to 30 GHz RFC High input linearity CTRL 1 dB power compression (P1dB): 28 dBm typical 50 VDD Third-order intercept (IP3): 52 dBm typical High power handling RF1 24 dBm through path Figure 1. 24 dBm terminated path ESD sensitivity: Class 1, 1 kV human body model (HBM) 20-terminal, 3 mm 3 mm land grid array package No low frequency spurious Radio frequency (RF) settling time (to 0.1 dB of final RF output): 6.2 s APPLICATIONS Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, electronic counter measures (ECMs) Broadband telecommunications systems GENERAL DESCRIPTION The ADRF5021 is a general-purpose single-pole, double-throw This broadband switch requires dual supply voltages, +3.3 V (SPDT) switch manufactured using a silicon process. It comes and 2.5 V, and provides CMOS/LVTTL logic-compatible in a 3 mm 3 mm, 20-terminal land grid array (LGA) package control. and provides high isolation and low insertion loss from 9 kHz to 30 GHz. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20162020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. DRIVER 14580-001ADRF5021 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ...................................................................................... 1 Typical Performance Characterics ..................................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7 General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept (IP3) 8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications .................................................................................... 3 Applications Information ............................................................. 10 Absolute Maximum Ratings ........................................................... 5 Evaluation Board ........................................................................ 10 Power Derating Curves ............................................................... 5 Probe Matrix Board ................................................................... 11 ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 12 Pin Configuration and Function Descriptions ............................ 6 Ordering Guide .......................................................................... 12 REVISION HISTORY 3/2020Rev. A to Rev. B 2/2017Rev. 0 to Rev. A Changes to Digital Control Inputs Parameter, Table 2 .............. 5 Changed VEN = 3.3 V to 5 V to VEN = 0 V or 3.3 V to 5 V ........... 3 Added Endnote 1, Table 2 Renumbered Sequentially ............... 5 Changes to Theory of Operation Section .................................... 10 7/2016Revision 0: Initial Version Rev. B Page 2 of 12