Silicon SPDT Switch, Nonreflective, 9 kHz to 44 GHz Data Sheet ADRF5027 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultrawideband frequency range: 9 kHz to 44 GHz Nonreflective design Low insertion loss GND 1 15 VSS 1.1 dB to 18 GHz 50 GND 2 14 EN 1.5 dB to 26 GHz 2.2 dB to 40 GHz RFC 3 DRIVER 13 GND 3.8 dB to 44 GHz 50 GND 4 12 CTRL High isolation 53 dB to 18 GHz GND 11 VDD 5 48 dB to 26 GHz 48 dB to 40 GHz 43 dB to 44 GHz High input linearity Figure 1. P1dB: 26 dBm typical IP3: 54 dBm typical High power handling 24 dBm insertion loss path 24 dBm isolation path All off state control No low frequency spurious signals 0.1 dB RF settling time: 6.0 s typical 20-terminal, 3 mm 3 mm LGA package Pin compatible with ADRF5026, fast switching version APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5027 is a nonreflective, single-pole, double-throw The ADRF5027 is pin compatible with the ADRF5026 fast (SPDT) radio frequency (RF) switch manufactured in a silicon switching version, which operates from 100 MHz to 44 GHz. process. The ADRF5027 RF ports are designed to match a characteristic The ADRF5027 operates from 9 kHz to 44 GHz with better impedance of 50 . For ultrawideband products, impedance than 3.8 dB of insertion loss and 43 dB of isolation. The matching on the RF transmission lines can further optimize ADRF5027 features an all off control, where both RF ports are high frequency insertion loss and return loss characteristics. in an isolation state. The ADRF5027 has a nonreflective design Refer to the Narrow-Band Impedance Matching section for an and both of the RF ports are internally terminated to 50 . example of a matched circuit that achieves a low insertion loss response of 2.2 dB from 28 GHz to 43 GHz. The ADRF5027 requires a dual-supply voltage of +3.3 V and 3.3 V. The device employs complimentary metal-oxide The ADRF5027 comes in a 20-terminal, 3 mm 3 mm, RoHS- semiconductor/low-voltage transistor-transistor logic compliant, land grid array (LGA) package and can operate (CMOS/LVTTL) logic-compatible controls. from 40C to +105C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20182020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com GND 6 20 GND GND 7 19 GND RF1 8 18 RF2 9 17 GND GND 10 16 GND GND 16768-001ADRF5027 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ...................................................................................... 1 Typical Performance Characteristics .............................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7 General Description ......................................................................... 1 Input Power Compressions and Third-Order Intercept .........8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications .................................................................................... 3 Applications Information ............................................................. 10 Electrical Specifications ............................................................... 3 Evaluation Board ........................................................................ 10 Absolute Maximum Ratings ........................................................... 5 Probe Matrix Board ................................................................... 11 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 13 Power Derating Curves ............................................................... 5 Ordering Guide .......................................................................... 13 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions ............................ 6 REVISION HISTORY 9/2020Rev. 0 to Rev. A Changes to Table 2 ........................................................................... 5 Changes to Theory of Operation Section ...................................... 9 Changes to Ordering Guide .......................................................... 12 7/2018Revision 0: Initial Version Rev. A Page 2 of 13