High Power, 20 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 5.0 GHz Data Sheet ADRF5132 FEATURES FUNCTIONAL BLOCK DIAGRAM ADRF5132 Reflective, 50 design Low insertion loss: 0.6 dB typical at 2.7 GHz High power handling at T = 105C CASE Long-term (>10 years operation) GND 1 12 GND Peak power: 43 dBm RF1 2 11 RF2 CW power: 38 dBm NIC 3 10 NIC LTE power average (8 dB PAR): 35 dBm 9 GND 4 GND Single event (<10 sec operation) LTE power average (8 dB PAR): 41 dBm High linearity P0.1dB: 42.5 dBm typical Figure 1. IP3: 65 dBm typical at 2.0 GHz to 4.0 GHz ESD ratings HBM: 2 kV, Class 2 CDM: 1.25 kV Single positive supply: 5 V Positive control, CMOS/TTL compatible 16-lead, 3 mm 3 mm LFCSP package APPLICATIONS Cellular/4G infrastructure Wireless infrastructure Military and high reliability applications Test equipment Pin diode replacement GENERAL DESCRIPTION The ADRF5132 is a high power, reflective, 0.7 GHz to 5.0 GHz, The on-chip circuitry operates at a single, positive supply silicon, single-pole, double-throw (SPDT) reflective switch in a voltage of 5 V and a typical supply current of 1.1 mA typical, leadless, surface-mount package. The switch is ideal for high making the ADRF5132 an ideal alternative to pin diode-based power and cellular infrastructure applications, like long-term switches. evolution (LTE) base stations. The ADRF5132 has high power The device is in a RoHS compliant, compact, 16-lead, 3 mm handling of 35 dBm LTE (average typical at 105C), a low insertion 3 mm LFCSP package. loss of 0.6 dB at 2.7 GHz, input third-order intercept of 65 dBm (typical), and 0.1 dB compression (P0.1dB) of 42.5 dBm. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20172019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. V GND DD GND GND RFC V CTL GND GND 16424-001 5 16 6 15 14 7 8 13ADRF5132 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 Insertion Loss, Isolation, Return Loss, Third-Order Intercept, and Power Compression ...............................................................6 General Description ......................................................................... 1 Theory of Operation .........................................................................8 Revision History ............................................................................... 2 Applications Information .................................................................9 Specifications ..................................................................................... 3 Evaluation Board ...........................................................................9 Absolute Maximum Ratings ............................................................ 4 Application Circuit ..................................................................... 10 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 12 Pin Configuration and Function Descriptions ............................. 5 REVISION HISTORY 8/2019Rev. A to Rev. B Changes to Figure 11 and Figure 12 ............................................... 7 Updated Outline Dimensions ....................................................... 12 4/2018Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Figure 2 and Table 2 ..................................................... 5 Changes to Figure 17 ...................................................................... 11 12/2017Revision 0: Initial Version Rev. B Page 2 of 12