Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End Data Sheet ADRF5547 FEATURES FUNCTIONAL BLOCK DIAGRAM ADRF5547 Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single-supply operation Gain High gain mode: 33 dB typical at 4.6 GHz GND 1 30 GND Low gain mode: 18 dB typical at 4.6 GHz GND 2 29 RxOUT-ChA ANT-ChA 3 28 GND Low noise figure GND 4 27 BP-ChA SWCTRL-ChAB 5 26 PD-ChAB High gain mode: 1.6 dB typical at 4.6 GHz SWVDD-ChAB 6 25 NIC GND 7 24 BP-ChB Low gain mode: 1.6 dB typical at 4.6 GHz ANT-ChB 8 23 GND GND 9 22 RxOUT-ChB High channel to channel isolation GND 10 21 GND Between RxOUT-ChA and RxOUT-ChB: 45 dB typical Between TERM-ChA and TERM-ChB: 53 dB typical Low insertion loss: 0.50 dB typical at 4.6 GHz High power handling at T = 105C CASE Full lifetime Figure 1. LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 31 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 40-lead, 6 mm 6 mm LFCSP APPLICATIONS Wireless infrastructure TDD massive multiple input and multiple output (MIMO) and active antenna systems TDD-based communication systems In low gain mode, one stage of the two-stage LNAs is in bypass, providing 18 dB gain at lower current of 36 mA. In power-down GENERAL DESCRIPTION mode, the LNAs are turned off and the device draws 12 mA. The ADRF5547 is a dual-channel, integrated RF, front end In transmit operation, when RF inputs are connected to a multichip module designed for time division duplexing (TDD) termination pin (TERM-ChA or TERM-ChB), the switch applications that operates from 3.7 GHz to 5.3 GHz. The provides a low insertion loss of 0.50 dB and handles long term ADRF5547 is configured in dual channels with a cascading evolution (LTE) average power (9 dB peak to average ratio two-stage low noise amplifier (LNA) and a high power silicon, (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single-pole, double-throw (SPDT) switch. single event (<10 sec) LNA protection operation. In high gain mode, the cascaded, two-stage LNA and switch The device comes in an RoHS compliant, compact, 40-lead, offer a low noise figure of 1.6 dB and high gain of 33 dB at 6 mm 6 mm LFCSP. 4.6 GHz with an output third order intercept point (OIP3) of 31 dBm (typical). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20192022 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 20790-001 GND 11 40 GND TERM-ChB 12 39 TERM-ChA NIC 13 38 NIC GND 14 37 GND GND 15 36 GND GND 16 35 GND VDD1-ChA VDD1-ChB 17 34 NIC 18 33 NIC NIC 19 32 NIC VDD2-ChB 20 31 VDD2-ChAADRF5547 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics .............................................8 Applications ...................................................................................... 1 Receive Operation, High Gain Mode .........................................8 General Description ......................................................................... 1 Receive Operation, Low Gain Mode ....................................... 10 Functional Block Diagram .............................................................. 1 Transmit Operation ................................................................... 12 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 13 Specifications .................................................................................... 3 Signal Path Select........................................................................ 13 Electrical Specifications ............................................................... 3 Biasing Sequence ........................................................................ 13 Absolute Maximum Ratings ........................................................... 5 Applications Information ............................................................. 14 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 15 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 15 Pin Configuration and Function Descriptions ............................ 6 Interface Schematics .................................................................... 7 REVISION HISTORY 1/2022Rev. A to Rev. B 6/2020Rev. 0 to Rev. A Changes to Charge Device Model (CDM) Parameter, Table 2 ....... 5 Changes to Theory of Operation Section ................................... 13 Changes to Figure 8, Figure 9, Figure 11, and Figure 13 ............ 8 Changes to Applications Information Section and Figure 28 ....... 14 Changes to Figure 14 and Figure 15 ................................................. 9 Changes to Figure 16, Figure 17, Figure 19, and Figure 21 ...... 10 10/2019Revision 0: Initial Version Changes to Figure 22 and Figure 23 ............................................ 11 Changes to Figure 24 ..................................................................... 12 Rev. B Page 2 of 15