ADRF5549BCPZN-R7 Analog Devices

Dual-Channel, 1.8 GHz to 2.8 GHz, Receiver Front End Data Sheet ADRF5549 FEATURES FUNCTIONAL BLOCK DIAGRAM ADRF5549 Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single-supply operation Gain High gain mode: 35 dB typical at 2.3 GHz GND 1 30 GND Low gain mode: 17 dB typical at 2.3 GHz GND 2 29 RxOUT-ChA ANT-ChA 3 28 GND Low noise figure GND 4 27 BP-ChA SWCTRL-ChAB 5 26 PD-ChAB High gain mode: 1.4 dB typical at 2.3 GHz SWVDD-ChAB 6 25 NIC GND 7 24 BP-ChB Low gain mode: 1.4 dB typical at 2.3 GHz ANT-ChB 8 23 GND GND 9 22 RxOUT-ChB High isolation GND 10 21 GND Between RxOUT-ChA and RxOUT-ChB: 50 dB typical Between TERM-ChA and TERM-ChB: 62 dB typical Low insertion loss: 0.6 dB typical at 2.3 GHz High power handling at T = 105C CASE Full lifetime Figure 1. LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 32 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 85 mA typical at 5V Low gain mode: 35 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 6 mm 6 mm, 40-lead LFCSP APPLICATIONS Wireless Infrastructure TDD massive multiple input and multiple output (MIMO) and active antenna systems TDD-based communication systems In low gain mode, one stage of the two-stage LNA is in bypass mode providing 17 dB of gain at a lower current of 35 mA. GENERAL DESCRIPTION In power-down mode, the LNAs are turned off, and the device The ADRF5549 is a dual-channel, integrated, RF front-end draws 12 mA. multichip module designed for time division duplexing (TDD) In transmit operation, when RF inputs are connected to a applications that operates from 1.8 GHz to 2.8 GHz. The termination pin (TERM-ChA or TERM-ChB), the switch ADRF5549 is configured in dual channels with a cascading, provides a low insertion loss of 0.6 dB and handles a long-term two-stage, low noise amplifier (LNA) and a high power, silicon evolution (LTE) full lifetime average (9 dB peak to average ratio single-pole, double-throw (SPDT) switch. (PAR)) of 40 dBm and 43 dBm for a 9 dB PAR LTE single event In high gain mode, the cascaded two-stage LNA and switch (<10 sec) average. The device comes in a RoHS-compliant, offer a low noise figure of 1.4 dB and a high gain of 35 dB with compact, 6 mm 6 mm, 40-lead, lead frame chip-scale package an output third-order intercept point (OIP3) of 32 dBm typical. (LFCSP). Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20192020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 20828-001 GND 11 40 GND TERM-ChB 12 39 TERM-ChA NIC 13 38 NIC GND 14 37 GND GND 15 36 GND GND 16 35 GND VDD1-ChB 17 34 VDD1-ChA NIC 18 33 NIC NIC 19 32 NIC VDD2-ChB 20 31 VDD2-ChAADRF5549 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................7 Applications ...................................................................................... 1 Typical Performance Characteristics .............................................8 General Description ......................................................................... 1 Receive Operation .........................................................................8 Functional Block Diagram .............................................................. 1 Transmit Operation ................................................................... 12 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 13 Specifications .................................................................................... 3 Signal Path Select........................................................................ 13 Electrical Specifications ............................................................... 3 Biasing Sequence ........................................................................ 13 Absolute Maximum Ratings ........................................................... 5 Applications Information ............................................................. 14 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 15 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 15 Pin Configuration and Function Descriptions ............................ 6 REVISION HISTORY 6/2020Rev. 0 to Rev. A Changes to Theory of Operation Section .................................... 13 Changes to Applications Information Section and Figure 28 ....... 14 9/2019Revision 0: Initial Version Rev. A Page 2 of 15