31 MHz, Dual Programmable Filters and Variable Gain Amplifiers Data Sheet ADRF6516 FEATURES FUNCTIONAL BLOCK DIAGRAM ENBL INP1 INM1 VPS COM VICM OFS1 VPS Matched pair of programmable filters and VGAs Continuous gain control range: 50 dB Digital gain control: 15 dB VPSD OPP1 6-pole Butterworth filter: 1 MHz to 31 MHz in 1 MHz steps, 1 dB corner frequency COMD OPM1 Preamplifier and postamplifier gain steps LE COM IMD3: >65 dBc for 1.5 V p-p composite output CLK GAIN SPI HD2, HD3: >65 dBc for 1.5 V p-p output DATA VOCM Differential input and output SDO COM Flexible output and input common-mode ranges Optional dc offset compensation loop COM OPM2 SPI programmable filter corners and gain steps VPS OPP2 ADRF6516 Power-down feature Single 3.3 V supply operation COM INP2 INM2 VPS COM OFDS OFS2 VPS APPLICATIONS Figure 1. Baseband IQ receivers Diversity receivers ADC drivers Point-to-point and point-to-multipoint radio Instrumentation Medical GENERAL DESCRIPTION The ADRF6516 is a matched pair of fully differential, low noise The variable gain amplifiers that follow the filters provide 50 dB and low distortion programmable filters and variable gain of continuous gain control with a slope of 15.5 mV/dB. Their amplifiers (VGAs). Each channel is capable of rejecting large maximum gains can be programmed to various values through out-of-band interferers while reliably boosting the desired signal, the SPI. The output buffers provide a differential output impedance thus reducing the bandwidth and resolution requirements on the of 30 and are capable of driving 2 V p-p into 1 k loads. The analog-to-digital converters (ADCs). The excellent matching output common-mode voltage defaults to VPS/2, but it can be between channels and their high spurious-free dynamic range adjusted down to 700 mV by driving the high impedance over all gain and bandwidth settings make the ADRF6516 ideal VOCM pin. Independent, built-in dc offset compensation loops for quadrature-based (IQ) communication systems with dense can be disabled if fully dc-coupled operation is desired. The constellations, multiple carriers, and nearby interferers. high-pass corner frequency is defined by external capacitors on the OFS1 and OFS2 pins and the VGA gain. The filters provide a six-pole Butterworth response with 1 dB corner frequencies programmable through the SPI port from The ADRF6516 operates from a 3.15 V to 3.45 V supply 1 MHz to 31 MHz in 1 MHz steps. The preamplifier that precedes and consumes a maximum supply current of 360 mA when the filters offers a SPI-programmable option of either 3 dB or 6 dB programmed to the highest bandwidth setting. When disabled, of gain. The preamplifier sets a differential input impedance of it consumes <9 mA. The ADRF6516 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 32-lead, 1600 and has a common-mode voltage that defaults to VPS/2 but can be driven from 1.1 V to 1.8 V. exposed paddle LFCSP. Performance is specified over the 40C to +85C temperature range. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09422-001ADRF6516 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Maximizing the Dynamic Range.............................................. 19 Applications ....................................................................................... 1 Key Parameters for Quadrature-Based Receivers .................. 20 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 21 General Description ......................................................................... 1 Basic Connections ...................................................................... 21 Revision History ............................................................................... 2 Supply Decoupling ..................................................................... 21 Specifications ..................................................................................... 3 Input Signal Path ........................................................................ 21 Timing Diagrams .......................................................................... 5 Output Signal Path ..................................................................... 21 Absolute Maximum Ratings ............................................................ 6 DC Offset Compensation Loop Enabled ................................ 21 ESD Caution .................................................................................. 6 Common-Mode Bypassing ....................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Serial Port Connections ............................................................. 22 Typical Performance Characteristics ............................................. 8 Enable/Disable Function ........................................................... 22 Register Map and Codes ................................................................ 15 Error Vector Magnitude (EVM) Performance ........................... 22 Theory of Operation ...................................................................... 16 EVM Test Setup .......................................................................... 22 Input Buffers ............................................................................... 16 Effect of Filter Bandwidth on EVM ......................................... 22 Programmable Filters ................................................................. 16 Effect of Output Voltage Levels on EVM ................................ 23 Variable Gain Amplifiers (VGAs) ............................................ 17 Effect of C Value on EVM ..................................................... 23 OFS Output Buffers/ADC Drivers ................................................... 17 Evaluation Board ............................................................................ 24 DC Offset Compensation Loop ................................................ 17 Evaluation Board Control Software ......................................... 24 Programming the Filters and Gains ......................................... 18 Schematics and Artwork ........................................................... 25 Noise Characteristics ................................................................. 18 Outline Dimensions ....................................................................... 29 Distortion Characteristics ......................................................... 19 Ordering Guide .......................................................................... 29 REVISION HISTORY 8/2017Rev. B to Rev. C Change to Figure 4 ........................................................................... 7 Updated Outline Dimensions ...................................................... 29 Changes to Ordering Guide Section ............................................ 29 2/2012Rev. A to Rev. B Changes to Figure 57 ...................................................................... 24 Changes to Figure 58 ...................................................................... 25 Added Figure 59 .............................................................................. 26 Changes to Figure 60 and Figure 61 ............................................. 27 Changes to Table 6 .......................................................................... 27 9/2011Revision A: Initial Version Rev. C Page 2 of 29