Integrated Dual RF Receivers Data Sheet ADRV9008-1 In addition to automatic gain control (AGC), the ADRV9008-1 also FEATURES features flexible external gain control modes, allowing dynamic Dual receivers gain control. Maximum receiver bandwidth: 200 MHz Fully integrated, fractional-N, RF synthesizers The received signals are digitized with a set of four, high dynamic Fully integrated clock synthesizer range, continuous time, sigma-delta (-) ADCs that provide Multichip phase synchronization for RF LO and baseband clocks inherent antialiasing. The combination of the direct conversion JESD204B datapath interface architecture (which does not suffer from out of band image Tuning range (center frequency): 75 MHz to 6000 MHz mixing) and the lack of aliasing reduces the requirements of the RF filters compared to the requirements of traditional intermediate APPLICATIONS frequency (IF) receivers. 3G/4G/5G FDD, macrocell base stations The fully integrated phase-locked loop (PLL) provides high Wideband active antenna systems performance, low power, fractional-N, RF synthesis for the Massive multiple input, multiple output (MIMO) receiver signal paths. An additional synthesizer generates the Phased array radar clocks needed for the converters, digital circuits, and serial Electronic warfare interface. A multichip synchronization mechanism synchronizes Military communications the phase of the RF local oscillator (LO) and baseband clocks Portable test equipment between multiple ADRV9008-1 chips. The ADRV9008-1 features GENERAL DESCRIPTION the isolation that high performance base station applications require. All voltage controlled oscillators (VCOs) and loop The ADRV9008-1 is a highly integrated, dual radio frequency (RF), filter components are integrated. agile receiver offering integrated synthesizers and digital signal processing functions. The IC delivers a versatile combination of The high speed JESD204B interface supports up to 12.288 Gbps high performance and low power consumption required by lane rates, resulting in a single lane per receiver in the widest 3G/4G/5G macrocell, frequency division duplex (FDD), base bandwidth mode. The interface also supports interleaved mode station applications. for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data The receive path consists of two independent, wide bandwidth, formats are supported. The floating point format allows internal direct conversion receivers with state-of-the-art dynamic range. AGC to be invisible to the demodulator device. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error The core of the ADRV9008-1 can be powered directly from correction (QEC), and digital filtering, eliminating the need for 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire these functions in the digital baseband. RF front-end control and serial port. Comprehensive power-down modes are included to several auxiliary functions, such as analog-to-digital converters minimize power consumption during normal use. The (ADCs), digital-to-analog converters (DACs), and general-purpose ADRV9008-1 is packaged in a 12 mm 12 mm, 196-ball chip input/outputs (GPIOs) for the power amplifier (PA), are also scale ball grid array (CSP BGA). integrated. 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Technical Support www.analog.com ADRV9008-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 47 Applications ....................................................................................... 1 Receivers ...................................................................................... 47 General Description ......................................................................... 1 Clock Input .................................................................................. 47 Revision History ............................................................................... 2 Synthesizers ................................................................................. 47 Functional Block Diagram .............................................................. 3 SPI ................................................................................................. 47 Specif icat ions ..................................................................................... 4 JTAG Boundary Scan ................................................................. 47 Current and Power Consumption Specifications ..................... 8 Power Supply Sequence ............................................................. 47 Timing Diagrams .......................................................................... 9 GPIO x Pins ............................................................................... 48 Absolute Maximum Ratings .......................................................... 10 Auxiliary Converters .................................................................. 48 Reflow Profile .............................................................................. 10 JESD204B Data Interface .......................................................... 48 Thermal Management ............................................................... 10 Applications Information .............................................................. 49 Thermal Resistance .................................................................... 10 PCB Layout and Power Supply Recommendations ............... 49 ESD Caution ................................................................................ 10 PCB Material and Stackup Selection ....................................... 49 Pin Configuration and Function Descriptions ........................... 11 Fanout and Trace Space Guidelines ......................................... 51 Typical Performance Characteristics ........................................... 17 Component Placement and Routing Guidelines ................... 52 75 MHz to 525 MHz Band ........................................................ 17 RF and JESD204B Transmission Line Layout ........................ 58 650 MHz to 3000 MHz Band .................................................... 25 Isolation Techniques Used on the ADRV9008-1W/PCBZ ... 60 3400 MHz to 4800 MHz Band .................................................. 33 RF Port Interface Information .................................................. 61 5100 MHz to 5900 MHz Band .................................................. 40 Outline Dimensions ....................................................................... 68 Receiver Input Impedance......................................................... 45 Ordering Guide .......................................................................... 68 Terminology .................................................................................... 46 REVISION HISTORY 9/2018Revision 0: Initial Version Rev. 0 Page 2 of 68