RF Agile Transceiver Data Sheet AD9364 FEATURES FUNCTIONAL BLOCK DIAGRAM RF 1 1 transceiver with integrated 12-bit DACs and ADCs RXB P, AD9364 Band: 70 MHz to 6.0 GHz RXB N Supports time division duplex (TDD) and frequency division RXA P, ADC RXA N duplex (FDD) operation P0 D11:D0 / RXC P, Rx LO RXC N TX D5:D0 Tunable channel bandwidth (BW): <200 kHz to 56 MHz P1 D11:D0 / 3-band receiver: 3 differential or 6 single-ended inputs TX MON Tx LO RX D5:D0 Superior receiver sensitivity with a noise figure of <2.5 dB TXA P, DAC TXA N Rx gain control TXB P, TXB N Real-time monitor and control signals for manual gain RADIO GPO SWITCHING Independent automatic gain control SPI 2-band differential output transmitter CTRL PLLs CLK OUT CTRL Highly linear broadband transmitter AUXADC AUXDACx XTALN Tx EVM: 40 dB NOTES Tx noise: 157 dBm/Hz noise floor 1. SPI, CTRL, P0 D11:D0 /TX D5:D0 , P1 D11:D0 /RX D5:D0 , AND RADIO SWITCHING CONTAIN MULTIPLE PINS. Tx monitor: 66 dB dynamic range with 1 dB accuracy Figure 1. Integrated fractional-N synthesizers 2.4 Hz maximum local oscillator (LO) step size Multichip synchronization CMOS/LVDS digital interface APPLICATIONS Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems GENERAL DESCRIPTION The AD9364 is a high performance, highly integrated radio fre- and 128-tap FIR filters to produce a 12-bit output signal at the quency (RF) Agile Transceiver designed for use in 3G and 4G base appropriate sample rate. station applications. Its programmability and wideband capability The transmitter uses a direct conversion architecture that achieves make it ideal for a broad range of transceiver applications. high modulation accuracy with ultralow noise. This transmitter The device combines an RF front end with a flexible mixed-signal design produces a Tx EVM of 40 dB, allowing significant system baseband section and integrated frequency synthesizers, simpli- margin for the external power amplifier (PA) selection. The on- fying design-in by providing a configurable digital interface to a board transmit (Tx) power monitor can be used as a power processor. The AD9364 operates in the 70 MHz to 6.0 GHz range, detector, enabling highly accurate Tx power measurements. covering most licensed and unlicensed bands. Channel bandwidths The fully integrated phase-locked loops (PLLs) provide low from less than 200 kHz to 56 MHz are supported. power fractional-N frequency synthesis for all Rx and Tx channels. The direct conversion receiver has state-of-the-art noise figure All VCO and loop filter components are integrated. and linearity. The receive (Rx) subsystem includes independent The core of the AD9364 can be powered directly from a 1.3 V automatic gain control (AGC), dc offset correction, quadrature regulator. The IC is controlled via a standard 4-wire serial port and correction, and digital filtering, thereby eliminating the need for four real-time input control pins. Comprehensive power-down these functions in the digital baseband. The AD9364 also has modes are included to minimize power consumption during flexible manual gain modes that can be externally controlled. normal use. The AD9364 is packaged in a 10 mm 10 mm, Two high dynamic range ADCs digitize the received I and Q 144-ball chip scale package ball grid array (CSP BGA). signals and pass them through configurable decimation filters Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. ADC DAC DAC DATA INTERFACE 11846-001AD9364 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 5.5 GHz Frequency Band .......................................................... 24 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 28 Functional Block Diagram .............................................................. 1 General......................................................................................... 28 General Description ......................................................................... 1 Receiver........................................................................................ 28 Revision History ............................................................................... 2 Transmitter .................................................................................. 28 Specifications ..................................................................................... 3 Clock Input Options .................................................................. 28 Current ConsumptionVDD Interface .................................. 7 Synthesizers ................................................................................. 29 Current ConsumptionVDDD1P3 DIG and VDDAx Digital Data Interface................................................................. 29 (Combination of All 1.3 V Supplies) ......................................... 8 Enable State Machine ..................................................................... 29 Absolute Maximum Ratings ..................................................... 10 SPI Interface ................................................................................ 30 Reflow Profile .............................................................................. 10 Control Pins ................................................................................ 30 Thermal Resistance .................................................................... 10 GPO Pins (GPO 3 to GPO 0) ................................................. 30 ESD Caution ................................................................................ 10 Auxiliary Converters .................................................................. 30 Pin Configuration and Function Descriptions ........................... 11 Powering the AD9364 ................................................................ 30 Typical Performance Characteristics ........................................... 15 Packaging and Ordering Information ......................................... 31 800 MHz Frequency Band ......................................................... 15 Outline Dimensions ................................................................... 31 2.4 GHz Frequency Band .......................................................... 20 Ordering Guide .......................................................................... 31 REVISION HISTORY 7/14Rev. B to Rev. C Changed CMOS VDD INTERFACE from 1.2 V (min)/2.5 V (max) to 1.14 V (min)/2.625 V (max) and Changed LVDS VDD INTERFACE from 1.8 V (min)/2.5 V (max) to 1.71 V (min)/2.625 V (max) Table 1......................................... 7 Added Powering the AD9364 Section ......................................... 30 2/14Revision B: Initial Version Rev. C Page 2 of 32