Critical Link, LLC MityDSP www.criticallink.com MityDSP Processor Card 28-AUG-2007 FEATURES APPLICATIONS TI TMS320C6711 Digital Signal Embedded Instrumentation Processor Rapid Development / Deployment - 200 MHz Embedded Digital Signal Processing - Hardware Floating Point Unit Industrial Instrumentation - 64 KB L2 cache Medical Instrumentation - 2 Integrated McBSPs Embedded Control Processing - JTAG Emulation/Debug On-Board Xilinx FPGA - XC3S400 - 300 MHz Clock Logic - 288 KBits Block RAM - 3,584 Slices - JTAG Interface/Debug 8 MB CPU SDRAM 2 MB NOR FLASH Standard SO-DIMM Interface - 100 FPGA User I/O Pins - 2 McBSP Interfaces (actual size) - DSP Emulator Interface - FPGA JTAG Interface - 3.3, 2.5, 1.23 V Power Interface DESCRIPTION The MityDSP is a highly configurable, very small form-factor processor card that features a Texas Instruments TMS320C6711 200 MHz Digital Signal Processor (DSP) tightly integrated with a Xilinx XC3S400 Spartan Field Programmable Gate Array (FPGA), FLASH and SDRAM memory subsystems. Both the DSP and the FGPA are capable of loading/executing programs and logic images developed by end users. The MityDSP provides a complete digital processing infrastructure necessary for embedded applications development. Users of the MityDSP are encouraged to develop applications and FPGA firmware using the MityDSP hardware and software development kit provided by Critical Link LLC. The development kit includes API libraries compatible with the TI Code Composer Studio compiler as well as FPGA netlist components compatible with the Xilinx ISE FPGA synthesis tool. The libraries provide the necessary functions needed to configure the MityDSP, program standalone MityDSP embedded applications, and interface with the various hardware components on the board. In addition, the libraries include several interface cores FPGA and DSP software modules designed to interface with various data converter modules (ADCs, DACs, LCD interfaces, etc) as well as bootloading and FLASH programming utilities. Figure 1 provides a top level block diagram of the MityDSP processor card. As shown in the figure, the primary interface to the MityDSP is through a standard SO-DIMM card edge interface. The interface provides power, DSP emulator, FPGA JTAG, synchronous serial connectivity, and up to 100 pins of configurable FPGA I/O for application defined 1 Copyright 2007, Critical Link LLC Critical Link, LLC MityDSP www.criticallink.com MityDSP Processor Card 28-AUG-2007 interfacing. Details of the SO-DIMM connector interface are included in the SO-DIMM Interface Description, below. Figure 1 MityDSP Block Diagram FPGA Bank I/O The MityDSP provides 100 lines of FPGA I/O directly to the SO-DIMM card edge interface. The 100 lines of FPGA I/O are distributed across TBD banks of the FPGA. These I/O lines and their associated logic are completely configurable within the FPGA, although typically a minimum of 2 lines are reserved for providing interface circuitry for field FLASH upgrades. With the Xilinx Spartan series of FPGA, a bank may be configured to operate on a different electrical interface standard based on input voltage and termination configurations. Of the 100 pins, 80 of the pins have been configured to use 3.3 Volt CMOS level logic. The remaining 20 pins, located on bank 7 of the FPGA, have been routed as differential pairs and may be configured as single ended 3.3 Volt or 2.5 Volt CMOS level logic, or may be configured as 2.5 Volt LVDS pairs. The configuration option is accomplished via resistor population on the board. Default configuration is for 3.3 Volt CMOS level logic. For pre-configured 2.5 Volt logic, please contact Critical Link sales representatives. 2 Copyright 2007, Critical Link LLC McBSP 1 McBSP 2 JTAG/Emulator ClkOut Reset 3.3 V 2.5 V 1.23 V GND JTAG Bank I/O (2.5 LVDS or 3.3 V CMOS) Bank I/O (3.3 V LVCMOS)