SHARC+ Dual-Core DSP with Arm Cortex-A5 ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587 19 mm 19 mm 349/529 BGA (0.8 pitch), RoHS compliant SYSTEM FEATURES Low system power across automotive temperature range Dual enhanced SHARC+ high performance floating-point cores MEMORY Up to 500 MHz per SHARC+ core Large on-chip L2 SRAM with ECC protection, up to 256 kB Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core On-chip L2 ROM (512 kB) with parity (optional ability to configure as cache) Two Level 3 (L3) interfaces optimized for low system power, 32-bit, 40-bit, and 64-bit floating-point support providing a 16-bit interface to DDR3 (supporting 1.5 V 32-bit fixed point capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices Byte, short-word, word, long-word addressed ADDITIONAL FEATURES Arm Cortex-A5 core Security and Protection 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle Cryptographic hardware accelerators 32 kB L1 instruction cache/32 kB L1 data cache Fast secure boot with IP protection 256 kB Level 2 (L2) cache with parity Support for Arm TrustZone Powerful DMA system Accelerators On-chip memory protection High performance pipelined FFT/IFFT engine Integrated safety features FIR, IIR, HAE, SINC offload engines AEC-Q100 qualified for automotive applications PERIPHERALS SYSTEM CONTROL SIGNAL ROUTING UNIT (SRU) SECURITY AND PROTECTION 22 PRECISION CLOCK CORE 0 CORE 1 CORE 2 SYSTEM PROTECTION (SPU) GENERATORS 2x DAI SYSTEM MEMORY ASRC FULL SPORT 2x PIN Arm 24 PAIRS 24 PROTECTION UNIT (SMPU) BUFFER 4028 S S FAULT MANAGEMENT Cortex-A5 21 S/PDIF Rx/Tx Arm TrustZone SECURITY 2 3 I C L1 CACHE DUAL CRC 6 32 kB L1 I-CACHE 2 LINK PORTS L1 SRAM (PARITY) L1 SRAM (PARITY) WATCHDOGS 32 kB L1 D-CACHE 2 SPI + 1 QUAD SPI 5 Mb (640 kB) 5 Mb (640 kB) OTP MEMORY L2 CACHE SRAM/CACHE SRAM/CACHE 3 UARTs 256 kB (PARITY) THERMAL MONITOR UNIT (TMU) 1 EPPI PROGRAM FLOW 3 ePWM SYS EVENT CORE 0 (GIC) 8 TIMERS + 1 COUNTER G SYS EVENT CORES 1-2 (SEC) ADC CONTROL MODULE SYSTEM CROSSBAR AND DMA SUBSYSTEM P TRIGGER ROUTING (TRU) (ACM) I O 10280 ASYNC MEMORY (16-BIT) CLOCK, RESET, AND POWER 2 CAN2.0 CLOCK GENERATION (CGU) SD/SDIO/eMMC L3 MEMORY SYSTEM SYSTEM CLOCK DISTRIBUTION UNIT (CDU) MLB 3-PIN INTERFACES L2 MEMORY ACCELERATION SRAM 2 EMAC REAL TIME CLOCK (RTC) DDR3 DDR3 DSP FUNCTIONS ROM ROM DDR2 DDR2 (ECC) (FFT/IFFT, FIR, IIR, HAE/SINC) 2 Mb 2 Mb SINC FILTER RESET CONTROL (RCU) LPDDR1 LPDDR1 2 Mb (256 kB) (256 kB) (256 kB) ENCRYPTION/DECRYPTION 8x SHARC FLAGS POWER MANAGEMENT (DPM) 10 2 USB 2.0 HS 16 16 DEBUG UNIT 6 MLB 6-PIN DATA DATA TM Arm CoreSight 7 PCIe2.0 (1 lane) WATCHPOINTS (SWU) HADC (8 CHAN, 12-BIT) 8 Figure 1. Processor Block Diagram SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587 TABLE OF CONTENTS System Features ....................................................... 1 GPIO Multiplexing for the 529-Ball CSP BGA Package ... 55 Memory ................................................................ 1 ADSP-SC58x/ADSP-2158x Designer Quick Reference .... 58 Additional Features .................................................. 1 Specifications ........................................................ 79 Table of Contents ..................................................... 2 Operating Conditions ........................................... 79 Revision History ...................................................... 2 Electrical Characteristics ....................................... 83 General Description ................................................. 3 HADC .............................................................. 87 ARM Cortex-A5 Processor ...................................... 5 TMU ................................................................ 87 SHARC Processor ................................................. 6 Absolute Maximum Ratings ................................... 88 SHARC+ Core Architecture .................................... 8 ESD Caution ...................................................... 88 System Infrastructure ........................................... 10 Timing Specifications ........................................... 89 System Memory Map ........................................... 11 Output Drive Currents ....................................... 153 Security Features ................................................ 14 Test Conditions ................................................ 155 Security Features Disclaimer .................................. 15 Environmental Conditions .................................. 157 Safety Features ................................................... 15 ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments .................................................... 158 Processor Peripherals ........................................... 15 Numerical by Ball Number .................................. 158 System Acceleration ............................................ 20 Alphabetical by Pin Name ................................... 160 System Design .................................................... 21 Configuration of the 349-Ball CSP BGA ................. 162 System Debug .................................................... 23 ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Development Tools ............................................. 24 Assignments .................................................... 163 Additional Information ........................................ 25 Numerical by Ball Number .................................. 163 Related Signal Chains .......................................... 25 Alphabetical by Pin Name ................................... 166 ADSP-SC58x/ADSP-2158x Detailed Signal Configuration of the 529-Ball CSP BGA ................. 169 Descriptions ...................................................... 26 Outline Dimensions .............................................. 170 349-Ball CSP BGA Signal Descriptions ....................... 31 Surface-Mount Design ........................................ 171 GPIO Multiplexing for the 349-Ball CSP BGA Package .. 40 Automotive Products ............................................ 172 529-Ball CSP BGA Signal Descriptions ....................... 43 Ordering Guide ................................................... 173 REVISION HISTORY 12/2018Rev. A to Rev. B Changes to ADSP-SC58x/ADSP-2158x Designer Quick Refer- ence .................................................................... 58 Changes to Additional Features ................................... 1 Deleted Package Information from Specifications ........... 79 Changes to Table 3, General Description ....................... 3 Changes to Operating Conditions .............................. 79 Changes to One Time Programmable Memory (OTP) .... 10 Changes to Table 28, Operating Conditions .................. 79 Changes to Table 7 and Table 8, System Memory Map .... 11 Changes to Table 29, Clock Related Operating Conditions 81 Changes to Housekeeping Analog-to-Digital Converter (HADC) .............................................................. 19 Changes to Total Internal Power Dissipation ................ 85 Changes to Media Local Bus (Media LB) ...................... 19 Changes Universal Serial Bus (USB) .......................... 138 Changes to ADSP-SC58x/ADSP-2158x Detailed Signal Descrip- Changes 10/100 EMAC Timing (ETH0 and ETH1) ...... 139 tions ................................................................... 26 Changes to Program Trace Macrocell (PTM) Timing .... 151 Changes to ADSP-SC58x/ADSP-2158x 349-Ball CSP BGA Sig- Changes to Test Conditions .................................... 155 nal Descriptions .................................................... 31 Changes to Automotive Products ............................. 172 Changes to ADSP-SC58x/ADSP-2158x 529-Ball CSP BGA Sig- nal Descriptions .................................................... 43 Rev. B Page 2 of 173 December 2018