JPEG2000 Video Codec
Data Sheet
ADV202
FEATURES APPLICATIONS
Complete single-chip JPEG2000 compression and Networked video and image distribution systems
decompression solution for video and still images Wireless video and image distribution
Patented SURF (spatial ultra-efficient recursive filtering) Image archival/retrieval
technology enables low power and low cost wavelet- Digital CCTV and surveillance systems
based compression Digital cinema systems
Supports both 9/7 and 5/3 wavelet transforms with up to Professional video editing and recording
6 levels of transform Digital still cameras
Programmable tile/image size with widths up to 2048 pixels in Digital camcorders
3-component 4:2:2 interleaved mode, and up to 4096 pixels
GENERAL DESCRIPTION
in single-component mode
The ADV202 is a single-chip JPEG2000 codec targeted for
Maximum tile/image width: 4096 pixels
video and high bandwidth image compression applications that
Video interface directly supporting ITU.R-BT656,
can benefit from the enhanced quality and feature set provided
SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M (525p),
by the JPEG2000 (J2K)ISO/IEC15444-1 image compression
ITU.R-BT1358 (625p) or any video format with a maximum
standard. The part implements the computationally intensive
input rate of 65 MSPS for irreversible mode or 40 MSPS for
operations of the JPEG2000 image compression standard as well
reversible mode
as providing fully compliant code-stream generation for most
Two or more ADV202s can be combined to support full-
applications.
frame SMPTE274M HDTV (1080i) or SMPTE296M (720p)
Flexible asynchronous SRAM-style host interface allows
The ADV202s dedicated video port provides glueless connection
glueless connection to most 16-/32-bit microcontrollers
to common digital video standards such as ITU.R-BT656,
and ASICs
SMPTE125M, SMPTE293M (525p), ITU.R-BT1358 (625p),
2.5 V to 3.3 V I/O and 1.5 V core supply
SMPTE274M (1080i), or SMPTE296M (720p). A variety of other
12 mm 12 mm 121-lead CSPBGA, speed grade 115 MHz, or
high speed, synchronous pixel and video formats can also be sup-
13 mm 13 mm 144-lead CSPBGA, speed grade 135 MHz, or
ported using the programmable framing and validation signals.
13 mm 13 mm 144-lead CSPBGA, speed grade 150 MHz
(continued on Page 4)
FUNCTIONAL BLOCK DIAGRAM
ADV202
WAVELET
PIXEL I/F
PIXEL I/F EC1 EC2 EC3
ENGINE
EXTERNAL
HOST I/F
DMA CTRL
PIXEL FIFO
INTERNAL BUS AND DMA ENGINE
CODE FIFO
ATTR FIFO
EMBEDDED
RISC
RAM ROM
PROCESSOR
SYSTEM
Figure 1.
Rev. D
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04723-001ADV202 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Embedded Processor System .................................................... 26
Applications ....................................................................................... 1 Memory System .......................................................................... 26
General Description ......................................................................... 1 Internal DMA Engine ................................................................ 26
Functional Block Diagram .............................................................. 1 ADV202 Interface........................................................................... 27
Revision History ............................................................................... 3 Video Interface (VDATA Bus) .................................................. 27
General Description ......................................................................... 4 Host Interface (HDATA Bus) ................................................... 27
JPEG2000 Feature Support.......................................................... 4 Direct and Indirect Registers .................................................... 27
Specifications ..................................................................................... 5 Control Access Registers ........................................................... 27
Supply Voltages and Current ...................................................... 5 Pin Configuration and Bus Sizes/Modes ................................ 28
Input/Output Specifications ........................................................ 5 Stage Register .............................................................................. 28
Clock and RESET Specifications ................................................ 6 JDATA Mode............................................................................... 28
External DMA Engine ............................................................... 28
Normal Host ModeRead Operation ...................................... 7
Internal Registers ............................................................................ 29
Normal Host ModeWrite Operation ..................................... 8
Direct Registers ........................................................................... 29
DREQ DACK
/ DMA ModeSingle FIFO Write Operation .. 9
Indirect Registers ........................................................................ 30
/ DMA ModeSingle FIFO Read Operation . 11
DREQ DACK
PLL ............................................................................................... 31
External DMA ModeFIFO Write, Burst Mode .................. 13
Hardware Boot ............................................................................ 31
External DMA ModeFIFO Read, Burst Mode ................... 14
Video Input Formats ...................................................................... 32
Streaming Mode (JDATA)FIFO Read/Write ...................... 16
Applications ..................................................................................... 34
VDATA Mode Timing ............................................................... 17
EncodeMultichip Mode ......................................................... 34
Raw Pixel Mode Timing ............................................................ 18
DecodeMultichip Master/Slave ............................................ 35
Absolute Maximum Ratings .......................................................... 19
Digital Still Camera/Camcorder .............................................. 35
Thermal Resistance .................................................................... 19
Encode/Decode SDTV Video Application ............................. 36
ESD Caution ................................................................................ 19
ASIC Application (32-Bit Host/32-Bit ASIC) ......................... 37
Pin BGA Assignments and Function Descriptions ................... 20
HIPI (Host InterfacePixel Interface) ................................... 38
Pin BGA Assignments ............................................................... 20
JDATA Interface ......................................................................... 38
Pin Function Descriptions ........................................................ 23
Outline Dimensions ....................................................................... 39
Theory of Operation ...................................................................... 26
Ordering Guide .......................................................................... 40
Wavelet Engine ........................................................................... 26
Entropy Codecs........................................................................... 26
Rev. D | Page 2 of 40