Wavescale Video Codec ADV212 FEATURES APPLICATIONS Implementation of a JPEG2000-compatible video CODEC for Networked video and image distribution systems video and still images through the ADV212 Wavescale Wireless video and image distribution video compression/decompression engine Image archival/retrieval Identical pinout and footprint to the ADV202 and support Digital CCTV and surveillance systems for all the functionality of the ADV202 Digital cinema systems Power reduction of at least 30% compared with ADV202 Professional video editing and recording JTAG/boundary scan support Digital still cameras Patented spatial ultraefficient recursive filtering (SURF) Digital camcorders technology for low power, low cost wavelet-based GENERAL DESCRIPTION compression The ADV212 Wavescale video compression/decompression Support for both 9/7 and 5/3 wavelet transforms with up to (CODEC) is a single-chip JPEG2000 CODEC targeted for video 5 levels of transform and high bandwidth image compression applications that can 9/7 wavelet support for tiles up to 1.048 million samples benefit from the enhanced quality and features provided by the 5/3 wavelet support for tiles up to 262,144 samples JPEG2000 (J2K) ISO/IEC15444-1 image compression standard. Video interface direct support for ITU-R BT.656, SMPTE 125M The part implements the computationally intensive operations PAL/NTSC, SMPTE 274M, SMPTE 293M (525p), and ITU-R of the JPEG2000 image compression standard and provides BT.1358 (625p) or any video format with a maximum input fully compliant code stream generation for most applications. rate of 65 MSPS for irreversible mode or 40 MSPS for reversible mode The dedicated video port of the ADV212 provides glueless con- Programmable tile/image size with widths of up to nection to common digital video standards such as ITU-R 4096 pixels in single-component mode maximum BT.656, SMPTE 125M, SMPTE 293M (525p), ITU-R BT.1358 tile/image height of 4096 pixels (625p), SMPTE 274M (1080i), and SMPTE 296M (720p). A Ability to combine 2 or more ADV212s to support full-frame variety of other high speed, synchronous pixel and video SMPTE 274M HDTV (1080i) or SMPTE 296M (720p) formats can also be supported by using the programmable Flexible, asynchronous SRAM-style host interface support framing and validation signals. for glueless connection to most 16-/32-bit microcontrollers The ADV212 is an upgrade version of the ADV202, which is and ASICs identical in pinout and footprint. It supports all of the func- 2.5 V or 3.3 V input/output and 1.5 V core supply tionality of the ADV202 and has the following additional 2 package and speed grade options options: JTAG/boundary scan support and power reduction of 12 mm 12 mm, 121-ball CSP BGA with a speed grade of at least 30% compared with the ADV202. 115 MHz 13 mm 13 mm, 144-ball CSP BGA with a speed grade of 150 MHz Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20062010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ADV212 TABLE OF CONTENTS Memory System .......................................................................... 25 Features .............................................................................................. 1 Internal DMA Engine ................................................................ 25 Applications ....................................................................................... 1 ADV212 Interfaces ......................................................................... 26 General Description ......................................................................... 1 Video Interface (VDATA Bus) .................................................. 26 Revision History ............................................................................... 2 Host Interface (HDATA Bus) ................................................... 26 JPEG2000 Feature Support .............................................................. 3 Direct and Indirect Registers .................................................... 26 Functional Block Diagram .............................................................. 3 Control Access Registers ........................................................... 27 Specifications ..................................................................................... 4 Pin Configuration and Bus Sizes/Modes ................................ 27 Supply Voltages and Current ...................................................... 4 Stage Register .............................................................................. 27 Input/Output Specifications ........................................................ 4 JDATA Mode ............................................................................... 27 Clock and RESET Specifications ................................................ 5 External DMA Engine ............................................................... 27 Normal Host ModeWrite Operation ..................................... 6 Internal Registers ............................................................................ 28 Normal Host ModeRead Operation ...................................... 7 Direct Registers ........................................................................... 28 DREQ DACK / DMA ModeSingle FIFO Write Operation .. 8 Indirect Registers ........................................................................ 29 DREQ DACK / DMA ModeSingle FIFO Read Operation . 10 PLL Registers .............................................................................. 30 External DMA ModeFIFO Write, Burst Mode .................. 12 Hardware Boot Modes and Power Considerations ............... 31 External DMA ModeFIFO Read, Burst Mode ................... 13 Video Input Formats ...................................................................... 32 Streaming Mode (JDATA)FIFO Read/Write ...................... 14 Applications Information .............................................................. 34 VDATA Mode Timing ............................................................... 15 EncodeMultichip Mode ......................................................... 34 Raw Pixel Mode Timing ............................................................ 17 DecodeMultichip Master/Slave ............................................ 35 JTAG Timing ............................................................................... 18 Digital Still Camera/Camcorder .............................................. 36 Absolute Maximum Ratings .......................................................... 19 Encode/Decode SDTV Video Application ............................. 37 Thermal Resistance .................................................................... 19 32-Bit Host Application ............................................................. 38 ESD Caution ................................................................................ 19 HIPI (Host InterfacePixel Interface) ................................... 39 Pin Configurations and Function Descriptions ......................... 20 JDATA Interface ......................................................................... 40 Theory of Operation ...................................................................... 25 Outline Dimensions ....................................................................... 41 Wavelet Engine ........................................................................... 25 Ordering Guide .......................................................................... 42 Entropy CODECs ....................................................................... 25 Embedded Processor System .................................................... 25 REVISION HISTORY 4/10Rev. A to Rev. B 4/08Rev. 0 to Rev. A Change to Table 1, Static Current Parameter ................................. 4 Added Wavescale Information .................................... Throughout Changes to Features Section............................................................ 1 Changes to Table 16 ........................................................................ 20 10/06Revision 0: Initial Version Changes to Video Interface (VDATA Bus) Section, Changes to Table 17 ............................................................................................ 26 Changes to Hardware Boot Modes Section ................................ 31 Changes to EncodeMultichip Mode Section .......................... 34 Rev. B Page 2 of 44