4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication Data Sheet ADV3002 FEATURES FUNCTIONAL BLOCK DIAGRAM SEL 1:0 TX EN RESETB 4 inputs, 1 output HDMI/DVI links SERIAL PARALLEL ADV3002 8 kV ESD protection on input pins AVCC I2C SDA AVEE CONFIG CONTROL HDMI 1.4a receive and transmit compliant I2C SCL INTERFACE LOGIC 2 I2C ADDR 1:0 Supports 250 Mbps to 2.25 Gbps data rates and beyond AVCC AVCC Supports 25 MHz to 225 MHz pixel clocks and beyond LOS Fully buffered unidirectional inputs/outputs + 4 + IN x CLK+ OUT CLK+ Switchable 50 on-chip input terminations with manual 4 IN x CLK OUT CLK + + IN x DATA2+ OUT DATA2+ or automatic control on channel switch 4 IN x DATA2 OUT DATA2 SWITCH + 4 + IN x DATA1+ CORE OUT DATA1+ Equalized inputs with low added jitter compensate for 4 EQ IN x DATA1 OUT DATA1 + + 4 IN x DATA0+ OUT DATA0+ more than 20 meters of HDMI cable at 2.25 Gbps 4 IN x DATA0 OUT DATA0 Loss of signal (LOS) detect circuit on TMDS clock TMDS Output disable feature for reduced power dissipation AVCC AVCC Bidirectional DDC buffers (SDA and SCL) 2 DDC xxx A 2 2 DDC xxx B SWITCH DDC SCL COM, EDID replication reduces component count, while enabling 2 CORE DDC xxx C DDC SDA COM 2 DDC xxx D simultaneous access to all HDMI sources 3.3V 3.3V 5 V combiner provides power to EDID replicator and CEC CEC IN CEC OUT buffer when local system power is off DDC/CEC Bidirectional buffered CEC line with integrated pull-up BIDIRECTIONAL resistors (26 k ) EDID ENABLE REPLICATOR Hot plug detect pulse low on channel switch with 2 CONTROL EDID SCL, EDID SDA EDID programmable pulse width or direct manual control P5V A 2 P5V B 5V Standards compatible: HDMI, DVI, HDCP, I C AMUXVCC COMBINER P5V C P5V D 80-lead, 14 mm 14 mm LQFP RoHS-compliant package EDID EEPROM INTERFACE HPD A APPLICATIONS HPD B HPD C HPD HPD D CONTROL Advanced television (HDTV) sets Projectors A/V receivers HOT PLUG DETECT Set-top boxes Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADV3002 is a complete HDMI/DVI link switch featuring 1. Input cable equalizer enables use of long cables at the input. equalized transition minimized differential signaling (TMDS) For a 24 AWG cable, the ADV3002 compensates for more inputs, ideal for systems with long cable runs. The ADV3002 than 20 meters at data rates of up to 2.25 Gbps. includes bidirectional buffering for the DDC bus and CEC line, 2. Auxiliary multiplexer isolates and buffers the DDC bus and with integrated pull-up resistors for the CEC line. Additionally, the CEC line, increasing total system capacitance limit. the ADV3002 includes an EDID replication function that enables 3. EDID replication eliminates the need for multiple EDID one EDID EEPROM to be shared for all four HDMI ports. EEPROMs. EDID can be loaded from a single external The ADV3002 is provided in a space-saving, 80-lead LQFP EEPROM or from a system microcontroller. surface-mount, Pb-free plastic package and is specified to 4. 5 V power combiner powers the EDID replicator and CEC operate over the 0C to 85C temperature range. buffer when local system power is off. 5. Integrated hot plug detect pulse low on channel switch with programmable pulse width or direct manual control. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07905-001ADV3002 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Buffers................................................................................ 13 Applications ....................................................................................... 1 EDID Replication ....................................................................... 13 General Description ......................................................................... 1 5 V Combiner ............................................................................. 15 Functional Block Diagram .............................................................. 1 CEC Buffer .................................................................................. 16 Product Highlights ........................................................................... 1 Hot Plug Detect Control ........................................................... 16 Revision History ............................................................................... 2 Loss of Signal Detect .................................................................. 16 Specifications ..................................................................................... 3 Serial Control Interface ................................................................. 17 TMDS Performance Specifications ............................................ 3 Reset ............................................................................................. 17 Auxiliary Channel Performance Specifications ....................... 3 Write Procedure .......................................................................... 17 Power Supply and Control Logic Specifications ...................... 4 Read Procedure........................................................................... 18 Absolute Maximum Ratings ............................................................ 5 Register Map ................................................................................... 19 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 21 ESD Caution .................................................................................. 5 HDMI Multiplexer for Advanced TV...................................... 21 Pin Configuration and Function Descriptions ............................. 6 Cable Lengths and Equalization ............................................... 24 Typical Performance Characteristics ............................................. 8 PCB Layout Guidelines.............................................................. 24 Theory of Operation ...................................................................... 12 Outline Dimensions ....................................................................... 27 TMDS Input Channels ............................................................... 12 Ordering Guide .......................................................................... 27 TMDS Output Channels ........................................................... 12 REVISION HISTORY 8/12Rev. A to Rev. B 8/11Rev. 0 to Rev. A Changed Data Rate = 3 Gbps to Changed Data Rate = 2.25 Gbps to Data Rate = 2.25 Gbps................................................... Throughout Data Rate = 3 Gbps ........................................................ Throughout Changes to Features Section and Product Highlights Section ... 1 Changes to Features Section and Product Highlights Section .... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 1 ............................................................................. 3 Changes to specifications statements in Typical Performance Changes to Figure 4 Caption and Figure 6 Caption ..................... 8 Added Figure 5 and Figure 7 Renumbered Sequentially ............ 8 Characteristics Section ..................................................................... 8 Changes to Theory of Operation Section .................................... 12 Moved Figure 8 and Figure 10 ......................................................... 9 Changes to Cable Lengths and Equalization Section and Changes to Figure 8 Caption and Figure 10 Caption ................... 9 PCB Layout Guidelines Section .................................................... 24 Added Figure 9 and Figure 11 ......................................................... 9 Added Unused DDC/CEC Buffers Section ................................. 26 Changes to Figure 12 and Figure 15 ............................................ 10 Changes to TMDS Input Channels Section and TMDS Output Channels Section ............................................................................ 12 Changes to Figure 31 ...................................................................... 16 Changes to Cable Lengths and Equalization Section ................ 24 12/08Revision 0: Initial Version Rev. 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