Closed Circuit TV Digital a Video Codec ADV611/ADV612 FEATURES levels. The chips integrate glueless video and host interfaces Programmable Quality Box with on-chip SRAM to permit low part count, system level Industrial Temperature Range (ADV612) implementations suitable for a broad range of applications. Hardware Frame Rate Reduction The ADV611/ADV612 are 100% bitstream compatible with 100% Bitstream Compatible with the ADV601 and the ADV601. The ADV611/ADV612 comes in a 120-lead ADV601LC LQFP package. Precise Compressed Bit Rate Control The ADV611/ADV612 are video encoders/decoders optimized Field Independent Compression for closed circuit TV (CCTV) applications. With the ADV611/ 8-Bit Video Interface Supports CCIR-656 and Multi- ADV612, you can define a portion of each video field to be at a plexed Philips Formats higher quality level relative to the rest of the field. This quality General Purpose 16- or 32-Bit Host Interface with box feature significantly increases compression of less impor- 512 Deep 32-Bit FIFO tant background details, while retaining the images overall PERFORMANCE context. Additionally, the unique subband coding architecture Real-Time Compression or Decompression of CCIR-601 of the ADV611/ADV612 offer many application-specific to Video: advantages. A review of the General Theory of Operation and 720 3 288 50 Fields/Sec PAL Applying the ADV611/ADV612 sections will help you get the 720 3 243 60 Fields/Sec NTSC most use out of the ADV611/ADV612 in any given application. Compression Ratios from Visually Loss-Less to 7500:1 The ADV611/ADV612 accept component digital video through Visually Loss-Less Compression At 4:1 on Natural the Video Interface and outputs a compressed bitstream though the Images (Typical) Host Interface in Encode Mode. While in Decode Mode, the APPLICATIONS ADV611/ADV612 accept compressed bitstream through the Host CCTV Cameras and Systems Interface and outputs component digital video through the Video Time-Lapse Video Tape Recorders Interface. The host accesses all of the ADV611/ADV612s control Time-Lapse Video Disk Recorders and status registers using the Host Interface. Figure 2 summarizes Wireless CCTV Cameras the basic function of the part. Fiber CCTV Systems (continued on page 2) ANALOG ADV7185 VIDEO DECODER SIGNAL SERIAL GENERAL DESCRIPTION OR PARALLEL ADV611/ OR ADSP-21xx The ADV611/ADV612 are low cost, single chip, dedicated func- BITSTREAM FOR ADV612 TRANSMISSION tion, all-digital-CMOS-VLSI devices capable of supporting IMAGE OR STORAGE SENSOR DIGITIZER visually loss-less to 7500:1 real-time compression and decom- QUALITY BOX CONTROLS SIGNAL FROM REMOTE SITE pression of CCIR-601 digital video at very high image quality Figure 1. Typical Application FUNCTIONAL BLOCK DIAGRAM LOCATION, SIZE AND CONTRAST CONTROL ADV611/ ON-CHIP ADV612 TRANSFORM SUBBAND STATISTICS BUFFER WAVELET 8 16/32 QUALITY DIGITAL QUANTIZER HOST COMPONENT FILTERS, BOX HOST VIDEO & ENTROPY I/O PORT VIDEO I/O DECIMATOR & CONTROL I/O PORT CODING & FIFO INTERPOLATOR DRAM BIN WIDTH CONTROL MANAGER 256K 3 16-BIT DRAM REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: ADV611/ADV612 TABLE OF CONTENTS GENERAL DESCRIPTION (Continued from page 1) This data sheet gives an overview of the ADV611/ADV612s functionality and provides details on designing the part into a VIDEO INTERFACE HOST INTERFACE system. The text of the data sheet is written for an audience with COMPRESSED VIDEO OUT a general knowledge of designing digital video systems. Where ADV611/ DIGITAL VIDEO IN (ENCODE) (ENCODE) ADV612 appropriate, additional sources of reference material are noted STATUS AND CONTROL VIDEO CODEC DIGITAL VIDEO throughout the data sheet. CCTV DIGITAL OUT (DECODE) COMPRESSED VIDEO IN (DECODE) GENERAL DESCRIPTION . 1 COMPARING THE ADV6xx FAMILY VIDEO CODECS . 3 Figure 2. Functional Block Diagram INTERNAL ARCHITECTURE 4 GENERAL THEORY OF OPERATION 4 The ADV611/ADV612 adheres to international standard References 5 CCIR-601 for studio quality digital video. The codec also sup- THE WAVELET KERNEL 5 ports a range of field sizes and rates providing high performance THE PROGRAMMABLE QUANTIZER . 8 in computer, PAL, NTSC, or still image environments. The THE RUN LENGTH CODER AND HUFFMAN CODER . 9 ADV611/ADV612 is designed only for real-time interlaced Encoding vs. Decoding 9 video full frames of video are formed and processed as two PROGRAMMERS MODEL . 9 independent fields of data. The ADV611/ADV612 supports the ADV611/ADV612 REGISTER DESCRIPTIONS 11 field rates and sizes in Table I. Note that the maximum active VIDEO AREA REGISTERS . 14 field size is 720 by 288. The maximum pixel rate is 13.50 MHz. PIN FUNCTION DESCRIPTIONS 18 The ADV611/ADV612 has a generic 16-/32-bit host interface Video Interface 21 that includes a 512-position, 32-bit wide FIFO for compressed Video FormatsCCIR-656 . 22 video. With additional external hardware, the ADV611/ADV612s Host Interface 23 DRAM Manager 23 host interface is suitable (when interfaced to other devices) for Compressed Data-Stream Definition . 24 moving compressed video over PCI, ISA, SCSI, SONET, 10 Base APPLYING THE ADV611/ADV612 30 T, ARCnet, HDSL, ADSL and a broad range of digital inter- Using the ADV611/ADV612 in Computer Applications 30 faces. For a full description of the Host Interface, see the Host Using the ADV611/ADV612 in Stand-Alone Applications 31 Interface section. Connecting the ADV611/ADV612 to Popular Video The compressed data rate is determined by the input data rate Decoders and Encoders 31 and the selected compression ratio. The ADV611/ADV612 can GETTING THE MOST OUT OF ADV611/ADV612 . 32 achieve a near constant compressed bit rate by using the current How Much Compression Can Be Expected 32 field statistics in the off-chip bin width calculator on the exter- Evaluation Board 32 nal DSP or Host. The process of calculating bin widths on a Software Codec . 32 DSP or Host can be adaptive, optimizing the compressed bit Field Rate Reduction . 32 rate in real time. This feature provides a near constant bit rate Edge Enhancement and Detection . 32 out of the host interface in spite of scene changes or other types Motion Detection . 32 ADV611/ADV612 SPECIFICATIONS 33 of source material changes that would otherwise create bit rate TEST CONDITIONS . 34 burst conditions. For more information on the quantizer, see TIMING PARAMETERS . 34 the Programmable Quantizer section. Clock Signal Timing . 34 The ADV611/ADV612 typically yields visually loss-less com- CCIR-656 Video Format Timing 35 pression on natural images at a 4:1 compression ratio. For more Multiplexed Philips Video Timing . 37 information on compression ratios, see the Getting the Most Host Interface (Indirect Address, Indirect Register Data, Out of the ADV611/ADV612 section. Desired image quality and Interrupt Mask/Status) Register Timing . 40 levels can vary widely in different applications, so it is advisable Host Interface (Compressed Data) Register Timing . 42 to evaluate image quality of known source material at different ADV611/ADV612 LQFP PINOUTS 44 compression ratios to find the best compression range for the ADV611/ADV612 PIN CONFIGURATION 45 application. The subband coding architecture of the ADV611/ OUTLINE DIMENSIONS 46 ADV612 provides a number of options to stretch compression ORDERING GUIDE 46 performance. These options are outlined in the Applying the ADV611/ADV612 section. Table I. ADV611/ADV612 Field Rates and Sizes Active Active Total Total Standard Region Region Region Region Field Rate Pixel Rate 1 2 Name Horizontal Vertical Horizontal Vertical (Hz) (MHz) CCIR-601/525 720 243 858 262.5 59.94 13.50 CCIR-601/625 720 288 864 312.5 50.00 13.50 NOTES 1 The maximum active field size is 720 by 288. 2 The maximum pixel rate is 13.5 MHz. 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