Digital PAL/NTSC Video Encoder with 10-Bit SSAF and Advanced Power Management ADV7170/ADV7171 Programmable LUMA delay FEATURES 1 Individual on/off control of each DAC ITU-R BT601/656 YCrCb to PAL/NTSC video encoder CCIR and square pixel operation High quality 10-bit video DACs Integrated subcarrier locking to external video source SSAF (super sub-alias filter) Color signal control/burst signal control Advanced power management features Interlaced/noninterlaced operation CGMS (copy generation management system) Complete on-chip video timing generator WSS (wide screen signalling) Programmable multimode master/slave operation Simultaneous Y, U, V, C output format 3 2 Macrovision AntiTaping Rev. 7.1 (ADV7170 only) NTSC M, PAL M/N , PAL B/D/G/H/I, PAL60 Closed captioning support Single 27 MHz clock required (2 oversampling) Teletext insertion port (PAL-WST) 80 dB video SNR On-board color bar generation 32-bit direct digital synthesizer for color subcarrier On-board voltage reference Multistandard video output support 2 2 2-wire serial MPU interface (I C-compatible and Fast I C) Composite (CVBS) Single supply 5 V or 3.3 V operation Components S-Video (Y/C), YUV, and RGB Small 44-lead MQFP/TQFP packages EuroSCART output (RGB + CVBS/LUMA) 4 Industrial temperature grade = 40C to +85C Component YUV + CHROMA Video input data port supports APPLICATIONS High performance DVD playback systems, portable video CCIR-656 4:2:2 8-bit parallel input format equipment including digital still cameras and laptop PCs, 4:2:2 16-bit parallel input format video games, PC video/multimedia and digital Programmable simultaneous composite and S-Video or RGB satellite/cable systems (set-top boxes/IRD) (SCART)/YUV video outputs 1 Programmable luma filters (low-pass PAL/NTSC ) notch, ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). extended (SSAF, CIF, and QCIF) 2 Throughout the document N is referenced to PAL- Combination -N. Programmable chroma filters (low-pass 0.65 MHz, 1.0 MHz, 3 Protected by U.S. Patents 4,631,603 , 4,577,216, 4,819,098 and other intellectual 1.2 MHz and 2.0 MHz , CIF and QCIF) property rights. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales Programmable VBI (vertical blanking interval) office for latest Macrovision version available. Programmable subcarrier frequency and phase 4 Refer to Table 8 for complete operating details. TTXREQ TTX M POWER 10 U 10 10-BIT MANAGEMENT CGMS AND WSS DAC D (PIN 27) TELETEXT L DAC CONTROL INSERTION T INSERTION YUV TO V AA 10 (SLEEP MODE) I BLOCK BLOCK RGB 10 P 10-BIT MATRIX DAC C (PIN 26) L DAC 10 RESET E 10 X 10-BIT 8 Y 8 9 9 COLOR E DAC B (PIN 31) PROGRAMMABLE ADD INTER- 10 DAC DATA R LUMINANCE SYNC POLATOR P7P0 4:2:2 TO YCrCb FILTER 8 4:4:4 TO U 10 U 8 8 8 INTER- YUV 10 INTER- PROGRAMMABLE ADD P15P8 POLATOR MATRIX 10-BIT 8 V 8 8 8 DAC A (PIN 32) POLATOR CHROMINANCE BURST 10 DAC V FILTER ADV7170/ADV7171 HSYNC 10 REAL-TIME 10 VIDEO TIMING FIELD/VSYNC 2 V I C MPU PORT CONTROL REF VOLTAGE GENERATOR SIN/COS CIRCUIT BLANK REFERENCE R DDS BLOCK SET CIRCUIT COMP CLOCK SCLOCK SDATA ALSB SCRESET/RTC GND Figure 1. Functional Block Diagram Protected by U.S. Patents 5,343,196 5,442,355 and other intellectual property rights. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781.461.3113 20022009 Analog Devices, Inc. All rights reserved. 00221-001ADV7170/ADV7171 TABLE OF CONTENTS Specif ications ..................................................................................... 4 Mode Register 1 MR1 (MR17 to MR10) ................................. 30 Dynamic Specifications ............................................................... 6 MR1 Bit Description .................................................................. 30 Timing Specifications .................................................................. 7 Mode Register 2 MR2 (MR27 to MR20) ................................. 30 Timing Diagrams.......................................................................... 9 MR2 Bit Description .................................................................. 30 Absolute Maximum Ratings .......................................................... 10 Mode Register 3 MR3 (MR37 to MR30) .................................... 32 Package Thermal Performance ................................................. 10 MR3 Bit Description .................................................................... 32 ESD Caution ................................................................................ 10 Mode Register 4 MR4 (MR47 to MR40) ................................. 33 Pin Configuration and Function Descriptions ........................... 11 MR4 Bit Description .................................................................. 33 General Description ....................................................................... 13 VSYNC 3H (MR43) .................................................................. 33 Data Path Description ................................................................ 13 Timing Mode Register 0 (TR07 to TR00) ............................... 33 Internal Filter Response ............................................................. 14 TR0 Bit Description ................................................................... 34 Typical Performance Characteristics ........................................... 15 Timing Mode Register 1 (TR17 to TR10) ............................... 34 Features ............................................................................................ 18 TR1 Bit Description ................................................................... 34 Color Bar Generation ................................................................ 18 Subcarrier Frequency Registers 0 to 3 (FSC3 to FSC0) ......... 35 Square Pixel Mode ...................................................................... 18 Subcarrier Phase Registers (FP7 to FP0) ................................. 35 Color Signal Control .................................................................. 18 Closed Captioning Even Field Data Register 1 to 0 (CED15 to CED0) .......................................................................................... 35 Burst Signal Control ................................................................... 18 Closed Captioning Odd Field Data Registers 1 to 0 (CCD15 NTSC Pedestal Control ............................................................. 18 to CCD0) ..................................................................................... 35 Pixel Timing Description .......................................................... 18 NTSC Pedestal/PAL Teletext Control Registers 3 to 0 (PCE15 to PCE0, PCO15 to PCO0)/(TXE15 to TXE0, TXO15 to Subcarrier Reset .......................................................................... 18 TXO0) .......................................................................................... 36 Real-Time Control ..................................................................... 18 Teletext Request Control Register TC07 (TC07 to TC00) .... 36 Video Timing Description ........................................................ 18 CGMS WSS Register 0 C/W0 (C/W07 to C/W00) .............. 36 Power-On Reset .......................................................................... 26 C/W0 Bit Description ................................................................ 36 SCH Phase Mode ........................................................................ 26 CGMS WSS Register 1 C/W1 (C/W17 to C/W10) .............. 37 MPU Port Description ............................................................... 26 C/W1 Bit Description ................................................................ 37 Register Accesses ........................................................................ 27 CGMS Data Bits (C/W17 to C/W16) ...................................... 37 Register Programming ................................................................... 28 CGMS WSS Register 2 C/W1 (C/W27 to C/W20) .............. 37 Subaddress Register (SR7 to SR0) ............................................ 28 C/W2 Bit Description ................................................................ 37 Register Select (SR5 to SR0) ...................................................... 28 Appendices ...................................................................................... 38 Mode Register 0 MR0 (MR07 to MR00) ................................. 28 Appendix 1Board Design and Layout Considerations...... 38 MR0 Bit Description .................................................................. 28 Rev. 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